mirror of
https://github.com/brain-hackers/u-boot-brain
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65e25bea59
In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
135 lines
2.9 KiB
C
135 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mc.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <linux/delay.h>
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#include <power/as3722.h>
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#include <power/pmic.h>
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#include "pinmux-config-nyan-big.h"
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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gpio_config_table(nyan_big_gpio_inits,
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ARRAY_SIZE(nyan_big_gpio_inits));
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pinmux_config_pingrp_table(nyan_big_pingrps,
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ARRAY_SIZE(nyan_big_pingrps));
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pinmux_config_drvgrp_table(nyan_big_drvgrps,
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ARRAY_SIZE(nyan_big_drvgrps));
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}
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int tegra_board_id(void)
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{
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static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
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TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
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-1};
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gpio_claim_vector(vector, "board_id%d");
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return gpio_get_values_as_int(vector);
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}
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int tegra_lcd_pmic_init(int board_id)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_PMIC,
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DM_DRIVER_GET(pmic_as3722), &dev);
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if (ret) {
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debug("%s: Failed to find PMIC\n", __func__);
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return ret;
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}
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if (board_id == 0)
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pmic_reg_write(dev, 0x00, 0x3c);
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else
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pmic_reg_write(dev, 0x00, 0x50);
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pmic_reg_write(dev, 0x12, 0x10);
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pmic_reg_write(dev, 0x0c, 0x07);
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pmic_reg_write(dev, 0x20, 0x10);
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return 0;
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}
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/* Setup required information for Linux kernel */
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static void setup_kernel_info(void)
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{
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struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
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/* The kernel graphics driver needs this region locked down */
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writel(0, &mc->mc_video_protect_bom);
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writel(0, &mc->mc_video_protect_size_mb);
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writel(1, &mc->mc_video_protect_reg_ctrl);
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}
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/*
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* We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
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* I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
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* Otherwise reading AHUB devices will hang when the kernel boots.
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*/
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static void enable_required_clocks(void)
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{
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static enum periph_id ids[] = {
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PERIPH_ID_I2S0,
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PERIPH_ID_I2S1,
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PERIPH_ID_I2S2,
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PERIPH_ID_I2S3,
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PERIPH_ID_I2S4,
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PERIPH_ID_AUDIO,
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PERIPH_ID_APBIF,
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PERIPH_ID_DAM0,
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PERIPH_ID_DAM1,
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PERIPH_ID_DAM2,
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PERIPH_ID_AMX0,
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PERIPH_ID_AMX1,
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PERIPH_ID_ADX0,
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PERIPH_ID_ADX1,
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PERIPH_ID_SPDIF,
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PERIPH_ID_AFC0,
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PERIPH_ID_AFC1,
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PERIPH_ID_AFC2,
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PERIPH_ID_AFC3,
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PERIPH_ID_AFC4,
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PERIPH_ID_AFC5,
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PERIPH_ID_EXTPERIPH1
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(ids); i++)
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clock_enable(ids[i]);
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udelay(2);
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for (i = 0; i < ARRAY_SIZE(ids); i++)
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reset_set_enable(ids[i], 0);
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}
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int nvidia_board_init(void)
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{
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clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
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clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000);
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/* For external MAX98090 audio codec */
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clock_external_output(1);
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setup_kernel_info();
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enable_required_clocks();
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return 0;
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}
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