mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
![Anton Vorontsov](/assets/img/avatar_default.png)
eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
565 lines
16 KiB
C
565 lines
16 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <ioports.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_esdhc.h>
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#include "bcsr.h"
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phys_size_t fixed_sdram(void);
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* QE_MUX_MDC */
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{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
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/* QE_MUX_MDIO */
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{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
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#if defined(CONFIG_SYS_UCC_RGMII_MODE)
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/* UCC_1_RGMII */
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{2, 11, 2, 0, 1}, /* CLK12 */
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{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
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{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
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{0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
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{0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
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{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
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{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
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{0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
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{0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
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{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
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{2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
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{2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
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/* UCC_2_RGMII */
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{2, 16, 2, 0, 3}, /* CLK17 */
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{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
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{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
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{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
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{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
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{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
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{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
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{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
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{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
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{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
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{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
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{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
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{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
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/* UCC_3_RGMII */
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{2, 11, 2, 0, 1}, /* CLK12 */
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{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
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{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
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{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
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{1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
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{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
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{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
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{1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
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{1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
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{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
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{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
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{2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
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{2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
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/* UCC_4_RGMII */
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{2, 16, 2, 0, 3}, /* CLK17 */
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{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
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{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
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{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
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{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
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{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
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{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
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{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
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{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
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{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
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{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
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{2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
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{2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
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#elif defined(CONFIG_SYS_UCC_RMII_MODE)
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/* UCC_1_RMII */
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{2, 15, 2, 0, 1}, /* CLK16 */
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{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
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{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
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{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
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{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
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{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
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/* UCC_2_RMII */
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{2, 15, 2, 0, 1}, /* CLK16 */
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{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
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{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
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{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
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{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
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{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
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{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
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/* UCC_3_RMII */
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{2, 15, 2, 0, 1}, /* CLK16 */
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{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
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{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
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{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
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{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
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{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
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{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
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/* UCC_4_RMII */
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{2, 15, 2, 0, 1}, /* CLK16 */
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{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
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{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
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{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
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{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
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{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
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{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
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#endif
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/* UART1 is muxed with QE PortF bit [9-12].*/
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{5, 12, 2, 0, 3}, /* UART1_SIN */
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{5, 9, 1, 0, 3}, /* UART1_SOUT */
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{5, 10, 2, 0, 3}, /* UART1_CTS_B */
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{5, 11, 1, 0, 2}, /* UART1_RTS_B */
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{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
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};
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void local_bus_init(void);
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int board_early_init_f (void)
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{
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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enable_8569mds_flash_write();
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#ifdef CONFIG_QE
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enable_8569mds_qe_uec();
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#endif
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#if CONFIG_SYS_I2C2_OFFSET
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/* Enable I2C2 signals instead of SD signals */
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volatile struct ccsr_gur *gur;
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gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
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gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
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gur->plppar1 |= PLPPAR1_I2C2_VAL;
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gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
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gur->plpdir1 |= PLPDIR1_I2C2_VAL;
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disable_8569mds_brd_eeprom_write_protect();
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#endif
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return 0;
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}
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int checkboard (void)
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{
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printf ("Board: 8569 MDS\n");
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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/*
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* Work around to stabilize DDR DLL MSYNC_IN.
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* Errata DDR9 seems to have been fixed.
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* This is now the workaround for Errata DDR11:
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* Override DLL = 1, Course Adj = 1, Tap Select = 0
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*/
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volatile ccsr_gur_t *gur =
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(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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out_be32(&gur->ddrdllcr, 0x81000000);
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udelay(200);
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#endif
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#ifdef CONFIG_SPD_EEPROM
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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phys_size_t fixed_sdram(void)
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{
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volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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uint d_init;
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
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out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
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out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
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out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
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out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
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#if defined (CONFIG_DDR_ECC)
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out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
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out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
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out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
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#endif
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udelay(500);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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udelay(1000);
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}
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debug("DDR: memory initialized\n\n");
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udelay(500);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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out_be32(&gur->lbiuiplldcr1, 0x00078080);
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if (clkdiv == 16)
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out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
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else if (clkdiv == 8)
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out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
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else if (clkdiv == 4)
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out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
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out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
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}
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#ifdef CONFIG_FSL_ESDHC
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/*
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* Because of an erratum in prototype boards it is impossible to use eSDHC
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* without disabling UART0 (which makes it quite easy to 'brick' the board
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* by simply issung 'setenv hwconfig esdhc', and not able to interact with
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* U-Boot anylonger).
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*
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* So, but default we assume that the board is a prototype, which is a most
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* safe assumption. There is no way to determine board revision from a
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* register, so we use hwconfig.
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*/
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static int prototype_board(void)
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{
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if (hwconfig_subarg("board", "rev", NULL))
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return hwconfig_subarg_cmp("board", "rev", "prototype");
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return 1;
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}
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static int esdhc_disables_uart0(void)
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{
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return prototype_board() ||
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hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
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}
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int board_mmc_init(bd_t *bd)
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{
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struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
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u8 bcsr6 = BCSR6_SD_CARD_1BIT;
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if (!hwconfig("esdhc"))
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return 0;
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printf("Enabling eSDHC...\n"
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" For eSDHC to function, I2C2 ");
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if (esdhc_disables_uart0()) {
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printf("and UART0 should be disabled.\n");
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printf(" Redirecting stderr, stdout and stdin to UART1...\n");
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console_assign(stderr, "eserial1");
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console_assign(stdout, "eserial1");
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console_assign(stdin, "eserial1");
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printf("Switched to UART1 (initial log has been printed to "
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"UART0).\n");
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bcsr6 |= BCSR6_SD_CARD_4BITS;
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} else {
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printf("should be disabled.\n");
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}
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/* Assign I2C2 signals to eSDHC. */
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clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
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PLPPAR1_ESDHC_VAL);
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clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
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PLPDIR1_ESDHC_VAL);
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/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
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setbits_8(&bcsr[6], bcsr6);
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return fsl_esdhc_mmc_init(bd);
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}
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static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
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{
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const char *status = "disabled";
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int off;
|
|
int err;
|
|
|
|
if (!hwconfig("esdhc"))
|
|
return;
|
|
|
|
if (!esdhc_disables_uart0())
|
|
goto disable_i2c2;
|
|
|
|
off = fdt_path_offset(blob, "serial0");
|
|
if (off < 0) {
|
|
printf("WARNING: could not find serial0 alias: %s.\n",
|
|
fdt_strerror(off));
|
|
goto disable_i2c2;
|
|
}
|
|
|
|
err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
|
|
if (err) {
|
|
printf("WARNING: could not set status for serial0: %s.\n",
|
|
fdt_strerror(err));
|
|
return;
|
|
}
|
|
|
|
disable_i2c2:
|
|
off = -1;
|
|
while (1) {
|
|
const u32 *idx;
|
|
int len;
|
|
|
|
off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
|
|
if (off < 0)
|
|
break;
|
|
|
|
idx = fdt_getprop(blob, off, "cell-index", &len);
|
|
if (!idx || len != sizeof(*idx))
|
|
continue;
|
|
|
|
if (*idx == 1) {
|
|
fdt_setprop(blob, off, "status", status,
|
|
strlen(status) + 1);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE1
|
|
static struct pci_controller pcie1_hose;
|
|
#endif /* CONFIG_PCIE1 */
|
|
|
|
int first_free_busno = 0;
|
|
|
|
#ifdef CONFIG_PCI
|
|
void
|
|
pci_init_board(void)
|
|
{
|
|
volatile ccsr_gur_t *gur;
|
|
uint io_sel;
|
|
uint host_agent;
|
|
|
|
gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
|
host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
|
|
|
#ifdef CONFIG_PCIE1
|
|
{
|
|
volatile ccsr_fsl_pci_t *pci;
|
|
struct pci_controller *hose;
|
|
int pcie_ep;
|
|
struct pci_region *r;
|
|
int pcie_configured;
|
|
|
|
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
|
|
hose = &pcie1_hose;
|
|
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
|
|
r = hose->regions;
|
|
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
|
|
|
|
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
|
|
printf ("\n PCIE connected to slot as %s (base address %x)",
|
|
pcie_ep ? "End Point" : "Root Complex",
|
|
(uint)pci);
|
|
|
|
if (pci->pme_msg_det) {
|
|
pci->pme_msg_det = 0xffffffff;
|
|
debug (" with errors. Clearing. Now 0x%08x",
|
|
pci->pme_msg_det);
|
|
}
|
|
printf ("\n");
|
|
|
|
/* outbound memory */
|
|
pci_set_region(r++,
|
|
CONFIG_SYS_PCIE1_MEM_BUS,
|
|
CONFIG_SYS_PCIE1_MEM_PHYS,
|
|
CONFIG_SYS_PCIE1_MEM_SIZE,
|
|
PCI_REGION_MEM);
|
|
|
|
/* outbound io */
|
|
pci_set_region(r++,
|
|
CONFIG_SYS_PCIE1_IO_BUS,
|
|
CONFIG_SYS_PCIE1_IO_PHYS,
|
|
CONFIG_SYS_PCIE1_IO_SIZE,
|
|
PCI_REGION_IO);
|
|
|
|
hose->region_count = r - hose->regions;
|
|
|
|
hose->first_busno=first_free_busno;
|
|
|
|
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
|
|
printf ("PCIE on bus %02x - %02x\n",
|
|
hose->first_busno,hose->last_busno);
|
|
|
|
first_free_busno=hose->last_busno+1;
|
|
|
|
} else {
|
|
printf (" PCIE: disabled\n");
|
|
}
|
|
}
|
|
#else
|
|
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
|
|
#endif
|
|
}
|
|
#endif /* CONFIG_PCI */
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
void ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
#if defined(CONFIG_SYS_UCC_RMII_MODE)
|
|
int nodeoff, off, err;
|
|
unsigned int val;
|
|
const u32 *ph;
|
|
const u32 *index;
|
|
|
|
/* fixup device tree for supporting rmii mode */
|
|
nodeoff = -1;
|
|
while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
|
|
"ucc_geth")) >= 0) {
|
|
err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
|
|
"clk16");
|
|
if (err < 0) {
|
|
printf("WARNING: could not set tx-clock-name %s.\n",
|
|
fdt_strerror(err));
|
|
break;
|
|
}
|
|
|
|
err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
|
|
"rmii");
|
|
if (err < 0) {
|
|
printf("WARNING: could not set phy-connection-type "
|
|
"%s.\n", fdt_strerror(err));
|
|
break;
|
|
}
|
|
|
|
index = fdt_getprop(blob, nodeoff, "cell-index", 0);
|
|
if (index == NULL) {
|
|
printf("WARNING: could not get cell-index of ucc\n");
|
|
break;
|
|
}
|
|
|
|
ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
|
|
if (ph == NULL) {
|
|
printf("WARNING: could not get phy-handle of ucc\n");
|
|
break;
|
|
}
|
|
|
|
off = fdt_node_offset_by_phandle(blob, *ph);
|
|
if (off < 0) {
|
|
printf("WARNING: could not get phy node %s.\n",
|
|
fdt_strerror(err));
|
|
break;
|
|
}
|
|
|
|
val = 0x7 + *index; /* RMII phy address starts from 0x8 */
|
|
|
|
err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
|
|
if (err < 0) {
|
|
printf("WARNING: could not set reg for phy-handle "
|
|
"%s.\n", fdt_strerror(err));
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
#ifdef CONFIG_PCIE1
|
|
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
|
|
#endif
|
|
fdt_board_fixup_esdhc(blob, bd);
|
|
}
|
|
#endif
|