mirror of
https://github.com/brain-hackers/u-boot-brain
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65dd74a674
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
76 lines
1.8 KiB
C
76 lines
1.8 KiB
C
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _U_BOOT_I386_H_
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#define _U_BOOT_I386_H_ 1
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/* cpu/.../cpu.c */
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int arch_cpu_init(void);
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int x86_cpu_init_r(void);
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int cpu_init_r(void);
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int x86_cpu_init_f(void);
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int cpu_init_f(void);
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void init_gd(gd_t *id, u64 *gdt_addr);
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void setup_gdt(gd_t *id, u64 *gdt_addr);
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int init_cache(void);
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int cleanup_before_linux(void);
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void panic_puts(const char *str);
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/* cpu/.../timer.c */
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void timer_isr(void *);
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typedef void (timer_fnc_t) (void);
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int register_timer_isr (timer_fnc_t *isr_func);
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unsigned long get_tbclk_mhz(void);
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void timer_set_base(uint64_t base);
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int pcat_timer_init(void);
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/* Architecture specific DRAM init */
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int dram_init(void);
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/* cpu/.../interrupts.c */
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int cpu_init_interrupts(void);
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/* board/.../... */
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int dram_init(void);
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int cleanup_before_linux(void);
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int x86_cleanup_before_linux(void);
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void x86_enable_caches(void);
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void x86_disable_caches(void);
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int x86_init_cache(void);
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void reset_cpu(ulong addr);
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ulong board_get_usable_ram_top(ulong total_size);
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void dram_init_banksize(void);
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int default_print_cpuinfo(void);
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void setup_pcat_compatibility(void);
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void isa_unmap_rom(u32 addr);
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u32 isa_map_rom(u32 bus_addr, int size);
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/* arch/x86/lib/... */
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int video_bios_init(void);
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void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
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void board_init_f_r(void) __attribute__ ((noreturn));
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/* Read the time stamp counter */
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static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
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{
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uint32_t high, low;
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__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
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return (((uint64_t)high) << 32) | low;
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}
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/* board/... */
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void timer_set_tsc_base(uint64_t new_base);
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uint64_t timer_get_tsc(void);
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void quick_ram_check(void);
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#endif /* _U_BOOT_I386_H_ */
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