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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
79 lines
1.7 KiB
C
79 lines
1.7 KiB
C
/*
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* (C) Copyright 2002-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#ifndef __ASSEMBLY__
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enum pei_boot_mode_t {
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PEI_BOOT_NONE = 0,
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PEI_BOOT_SOFT_RESET,
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PEI_BOOT_RESUME,
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};
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struct memory_area {
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uint64_t start;
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uint64_t size;
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};
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struct memory_info {
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int num_areas;
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uint64_t total_memory;
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uint64_t total_32bit_memory;
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struct memory_area area[CONFIG_NR_DRAM_BANKS];
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};
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/* Architecture-specific global data */
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struct arch_global_data {
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struct global_data *gd_addr; /* Location of Global Data */
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uint8_t x86; /* CPU family */
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uint8_t x86_vendor; /* CPU vendor */
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uint8_t x86_model;
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uint8_t x86_mask;
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uint32_t x86_device;
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uint64_t tsc_base; /* Initial value returned by rdtsc() */
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uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
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uint32_t tsc_prev; /* For show_boot_progress() */
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uint32_t tsc_mhz; /* TSC frequency in MHz */
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void *new_fdt; /* Relocated FDT */
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uint32_t bist; /* Built-in self test value */
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struct pci_controller *hose; /* PCI hose for early use */
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enum pei_boot_mode_t pei_boot_mode;
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const struct pch_gpio_map *gpio_map; /* board GPIO map */
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struct memory_info meminfo; /* Memory information */
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};
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#endif
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#include <asm-generic/global_data.h>
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#ifndef __ASSEMBLY__
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static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)
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{
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gd_t *gd_ptr;
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asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
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return gd_ptr;
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}
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#define gd get_fs_gd_ptr()
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#endif
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/*
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* Our private Global Data Flags
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*/
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#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */
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#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */
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#define DECLARE_GLOBAL_DATA_PTR
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#endif /* __ASM_GBL_DATA_H */
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