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![Simon Glass](/assets/img/avatar_default.png)
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
572 lines
16 KiB
C
572 lines
16 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2010,2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* Portions from Coreboot mainboard/google/link/romstage.c
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/processor.h>
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#include <asm/gpio.h>
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#include <asm/global_data.h>
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#include <asm/pci.h>
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#include <asm/arch/me.h>
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#include <asm/arch/pei_data.h>
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#include <asm/arch/pch.h>
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#include <asm/post.h>
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#include <asm/arch/sandybridge.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* This function looks for the highest region of memory lower than 4GB which
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* has enough space for U-Boot where U-Boot is aligned on a page boundary.
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* It overrides the default implementation found elsewhere which simply
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* picks the end of ram, wherever that may be. The location of the stack,
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* the relocation address, and how far U-Boot is moved by relocation are
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* set in the global data structure.
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*/
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ulong board_get_usable_ram_top(ulong total_size)
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{
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struct memory_info *info = &gd->arch.meminfo;
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uintptr_t dest_addr = 0;
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struct memory_area *largest = NULL;
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int i;
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/* Find largest area of memory below 4GB */
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for (i = 0; i < info->num_areas; i++) {
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struct memory_area *area = &info->area[i];
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if (area->start >= 1ULL << 32)
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continue;
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if (!largest || area->size > largest->size)
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largest = area;
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}
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/* If no suitable area was found, return an error. */
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assert(largest);
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if (!largest || largest->size < (2 << 20))
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panic("No available memory found for relocation");
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dest_addr = largest->start + largest->size;
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return (ulong)dest_addr;
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}
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void dram_init_banksize(void)
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{
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struct memory_info *info = &gd->arch.meminfo;
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int num_banks;
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int i;
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for (i = 0, num_banks = 0; i < info->num_areas; i++) {
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struct memory_area *area = &info->area[i];
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if (area->start >= 1ULL << 32)
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continue;
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gd->bd->bi_dram[num_banks].start = area->start;
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gd->bd->bi_dram[num_banks].size = area->size;
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num_banks++;
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}
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}
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static const char *const ecc_decoder[] = {
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"inactive",
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"active on IO",
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"disabled on IO",
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"active"
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};
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/*
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* Dump in the log memory controller configuration as read from the memory
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* controller registers.
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*/
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static void report_memory_config(void)
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{
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u32 addr_decoder_common, addr_decode_ch[2];
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int i;
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addr_decoder_common = readl(MCHBAR_REG(0x5000));
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addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
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addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
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debug("memcfg DDR3 clock %d MHz\n",
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(readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
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debug("memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
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debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
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debug(" enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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debug(" rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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debug(" DIMMA %d MB width x%d %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? 16 : 8,
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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debug(" DIMMB %d MB width x%d %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 20) & 1) ? 16 : 8,
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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static void post_system_agent_init(struct pei_data *pei_data)
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{
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/* If PCIe init is skipped, set the PEG clock gating */
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if (!pei_data->pcie_init)
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setbits_le32(MCHBAR_REG(0x7010), 1);
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}
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static asmlinkage void console_tx_byte(unsigned char byte)
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{
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#ifdef DEBUG
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putc(byte);
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#endif
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}
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/**
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* Find the PEI executable in the ROM and execute it.
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*
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* @param pei_data: configuration data for UEFI PEI reference code
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*/
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int sdram_initialise(struct pei_data *pei_data)
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{
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unsigned version;
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const char *data;
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uint16_t done;
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int ret;
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report_platform_info();
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/* Wait for ME to be ready */
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ret = intel_early_me_init();
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if (ret)
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return ret;
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ret = intel_early_me_uma_size();
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if (ret < 0)
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return ret;
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debug("Starting UEFI PEI System Agent\n");
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/* If MRC data is not found we cannot continue S3 resume. */
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if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
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debug("Giving up in sdram_initialize: No MRC data\n");
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outb(0x6, PORT_RESET);
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cpu_hlt();
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}
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/* Pass console handler in pei_data */
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pei_data->tx_byte = console_tx_byte;
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debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
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data = (char *)CONFIG_X86_MRC_START;
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if (data) {
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int rv;
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int (*func)(struct pei_data *);
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debug("Calling MRC at %p\n", data);
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post_code(POST_PRE_MRC);
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func = (int (*)(struct pei_data *))data;
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rv = func(pei_data);
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post_code(POST_MRC);
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if (rv) {
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switch (rv) {
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case -1:
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printf("PEI version mismatch.\n");
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break;
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case -2:
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printf("Invalid memory frequency.\n");
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break;
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default:
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printf("MRC returned %x.\n", rv);
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}
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printf("Nonzero MRC return value.\n");
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return -EFAULT;
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}
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} else {
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printf("UEFI PEI System Agent not found.\n");
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return -ENOSYS;
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}
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#if CONFIG_USBDEBUG
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/* mrc.bin reconfigures USB, so reinit it to have debug */
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early_usbdebug_init();
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#endif
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version = readl(MCHBAR_REG(0x5034));
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debug("System Agent Version %d.%d.%d Build %d\n",
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version >> 24 , (version >> 16) & 0xff,
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(version >> 8) & 0xff, version & 0xff);
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/*
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* Send ME init done for SandyBridge here. This is done inside the
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* SystemAgent binary on IvyBridge
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*/
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done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
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done &= BASE_REV_MASK;
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if (BASE_REV_SNB == done)
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intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
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else
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intel_early_me_status();
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post_system_agent_init(pei_data);
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report_memory_config();
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return 0;
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}
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static int copy_spd(struct pei_data *peid)
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{
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const int gpio_vector[] = {41, 42, 43, 10, -1};
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int spd_index;
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const void *blob = gd->fdt_blob;
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int node, spd_node;
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int ret, i;
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for (i = 0; ; i++) {
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if (gpio_vector[i] == -1)
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break;
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ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
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if (ret) {
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debug("%s: Could not request gpio %d\n", __func__,
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gpio_vector[i]);
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return ret;
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}
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}
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spd_index = gpio_get_values_as_int(gpio_vector);
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debug("spd index %d\n", spd_index);
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node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
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if (node < 0) {
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printf("SPD data not found.\n");
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return -ENOENT;
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}
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for (spd_node = fdt_first_subnode(blob, node);
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spd_node > 0;
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spd_node = fdt_next_subnode(blob, spd_node)) {
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const char *data;
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int len;
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if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
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continue;
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data = fdt_getprop(blob, spd_node, "data", &len);
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if (len < sizeof(peid->spd_data[0])) {
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printf("Missing SPD data\n");
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return -EINVAL;
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}
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debug("Using SDRAM SPD data for '%s'\n",
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fdt_get_name(blob, spd_node, NULL));
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memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
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break;
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}
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if (spd_node < 0) {
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printf("No SPD data found for index %d\n", spd_index);
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return -ENOENT;
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}
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return 0;
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}
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/**
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* add_memory_area() - Add a new usable memory area to our list
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*
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* Note: @start and @end must not span the first 4GB boundary
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*
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* @info: Place to store memory info
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* @start: Start of this memory area
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* @end: End of this memory area + 1
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*/
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static int add_memory_area(struct memory_info *info,
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uint64_t start, uint64_t end)
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{
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struct memory_area *ptr;
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if (info->num_areas == CONFIG_NR_DRAM_BANKS)
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return -ENOSPC;
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ptr = &info->area[info->num_areas];
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ptr->start = start;
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ptr->size = end - start;
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info->total_memory += ptr->size;
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if (ptr->start < (1ULL << 32))
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info->total_32bit_memory += ptr->size;
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debug("%d: memory %llx size %llx, total now %llx / %llx\n",
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info->num_areas, ptr->start, ptr->size,
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info->total_32bit_memory, info->total_memory);
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info->num_areas++;
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return 0;
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}
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/**
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* sdram_find() - Find available memory
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*
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* This is a bit complicated since on x86 there are system memory holes all
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* over the place. We create a list of available memory blocks
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*/
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static int sdram_find(pci_dev_t dev)
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{
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struct memory_info *info = &gd->arch.meminfo;
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uint32_t tseg_base, uma_size, tolud;
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uint64_t tom, me_base, touud;
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uint64_t uma_memory_base = 0;
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uint64_t uma_memory_size;
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unsigned long long tomk;
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uint16_t ggc;
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/* Total Memory 2GB example:
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*
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* 00000000 0000MB-1992MB 1992MB RAM (writeback)
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* 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
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* 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
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* 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
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* 7f200000 2034MB TOLUD
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* 7f800000 2040MB MEBASE
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* 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
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* 80000000 2048MB TOM
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* 100000000 4096MB-4102MB 6MB RAM (writeback)
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*
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* Total Memory 4GB example:
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*
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* 00000000 0000MB-2768MB 2768MB RAM (writeback)
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* ad000000 2768MB-2776MB 8MB TSEG (SMRR)
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* ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
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* ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
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* afa00000 2810MB TOLUD
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* ff800000 4088MB MEBASE
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* ff800000 4088MB-4096MB 8MB ME UMA (uncached)
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* 100000000 4096MB TOM
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* 100000000 4096MB-5374MB 1278MB RAM (writeback)
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* 14fe00000 5368MB TOUUD
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*/
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/* Top of Upper Usable DRAM, including remap */
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touud = pci_read_config32(dev, TOUUD+4);
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touud <<= 32;
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touud |= pci_read_config32(dev, TOUUD);
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/* Top of Lower Usable DRAM */
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tolud = pci_read_config32(dev, TOLUD);
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/* Top of Memory - does not account for any UMA */
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tom = pci_read_config32(dev, 0xa4);
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tom <<= 32;
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tom |= pci_read_config32(dev, 0xa0);
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debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
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/* ME UMA needs excluding if total memory <4GB */
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me_base = pci_read_config32(dev, 0x74);
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me_base <<= 32;
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me_base |= pci_read_config32(dev, 0x70);
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debug("MEBASE %llx\n", me_base);
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/* TODO: Get rid of all this shifting by 10 bits */
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tomk = tolud >> 10;
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if (me_base == tolud) {
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/* ME is from MEBASE-TOM */
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uma_size = (tom - me_base) >> 10;
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/* Increment TOLUD to account for ME as RAM */
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tolud += uma_size << 10;
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/* UMA starts at old TOLUD */
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uma_memory_base = tomk * 1024ULL;
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uma_memory_size = uma_size * 1024ULL;
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debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
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}
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/* Graphics memory comes next */
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ggc = pci_read_config16(dev, GGC);
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if (!(ggc & 2)) {
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debug("IGD decoded, subtracting ");
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/* Graphics memory */
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uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
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debug("%uM UMA", uma_size >> 10);
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tomk -= uma_size;
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uma_memory_base = tomk * 1024ULL;
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uma_memory_size += uma_size * 1024ULL;
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/* GTT Graphics Stolen Memory Size (GGMS) */
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uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
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tomk -= uma_size;
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uma_memory_base = tomk * 1024ULL;
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uma_memory_size += uma_size * 1024ULL;
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debug(" and %uM GTT\n", uma_size >> 10);
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}
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/* Calculate TSEG size from its base which must be below GTT */
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tseg_base = pci_read_config32(dev, 0xb8);
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uma_size = (uma_memory_base - tseg_base) >> 10;
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tomk -= uma_size;
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uma_memory_base = tomk * 1024ULL;
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uma_memory_size += uma_size * 1024ULL;
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debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
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debug("Available memory below 4GB: %lluM\n", tomk >> 10);
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/* Report the memory regions */
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add_memory_area(info, 1 << 20, 2 << 28);
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add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
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add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
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add_memory_area(info, 1ULL << 32, touud);
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/*
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* If >= 4GB installed then memory from TOLUD to 4GB
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* is remapped above TOM, TOUUD will account for both
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*/
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if (touud > (1ULL << 32ULL)) {
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debug("Available memory above 4GB: %lluM\n",
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(touud >> 20) - 4096);
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}
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return 0;
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}
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static void rcba_config(void)
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{
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/*
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* GFX INTA -> PIRQA (MSI)
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* D28IP_P3IP WLAN INTA -> PIRQB
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* D29IP_E1P EHCI1 INTA -> PIRQD
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* D26IP_E2P EHCI2 INTA -> PIRQF
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* D31IP_SIP SATA INTA -> PIRQF (MSI)
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* D31IP_SMIP SMBUS INTB -> PIRQH
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* D31IP_TTIP THRT INTC -> PIRQA
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* D27IP_ZIP HDA INTA -> PIRQA (MSI)
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*
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* TRACKPAD -> PIRQE (Edge Triggered)
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* TOUCHSCREEN -> PIRQG (Edge Triggered)
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*/
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/* Device interrupt pin register (board specific) */
|
|
writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
|
|
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
|
|
writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
|
|
writel(INTA << D29IP_E1P, RCB_REG(D29IP));
|
|
writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
|
|
writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
|
|
writel(INTA << D26IP_E2P, RCB_REG(D26IP));
|
|
writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
|
|
writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
|
|
|
|
/* Device interrupt route registers */
|
|
writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
|
|
writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
|
|
writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
|
|
writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
|
|
writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
|
|
writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
|
|
writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
|
|
|
|
/* Enable IOAPIC (generic) */
|
|
writew(0x0100, RCB_REG(OIC));
|
|
/* PCH BWG says to read back the IOAPIC enable register */
|
|
(void)readw(RCB_REG(OIC));
|
|
|
|
/* Disable unused devices (board specific) */
|
|
setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
struct pei_data pei_data __aligned(8) = {
|
|
.pei_version = PEI_VERSION,
|
|
.mchbar = DEFAULT_MCHBAR,
|
|
.dmibar = DEFAULT_DMIBAR,
|
|
.epbar = DEFAULT_EPBAR,
|
|
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
|
|
.smbusbar = SMBUS_IO_BASE,
|
|
.wdbbar = 0x4000000,
|
|
.wdbsize = 0x1000,
|
|
.hpet_address = CONFIG_HPET_ADDRESS,
|
|
.rcba = DEFAULT_RCBABASE,
|
|
.pmbase = DEFAULT_PMBASE,
|
|
.gpiobase = DEFAULT_GPIOBASE,
|
|
.thermalbase = 0xfed08000,
|
|
.system_type = 0, /* 0 Mobile, 1 Desktop/Server */
|
|
.tseg_size = CONFIG_SMM_TSEG_SIZE,
|
|
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
|
|
.ec_present = 1,
|
|
.ddr3lv_support = 1,
|
|
/*
|
|
* 0 = leave channel enabled
|
|
* 1 = disable dimm 0 on channel
|
|
* 2 = disable dimm 1 on channel
|
|
* 3 = disable dimm 0+1 on channel
|
|
*/
|
|
.dimm_channel0_disabled = 2,
|
|
.dimm_channel1_disabled = 2,
|
|
.max_ddr3_freq = 1600,
|
|
.usb_port_config = {
|
|
/*
|
|
* Empty and onboard Ports 0-7, set to un-used pin
|
|
* OC3
|
|
*/
|
|
{ 0, 3, 0x0000 }, /* P0= Empty */
|
|
{ 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
|
|
{ 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
|
|
{ 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
|
|
{ 0, 3, 0x0000 }, /* P4= Empty */
|
|
{ 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
|
|
{ 0, 3, 0x0000 }, /* P6= Empty */
|
|
{ 0, 3, 0x0000 }, /* P7= Empty */
|
|
/*
|
|
* Empty and onboard Ports 8-13, set to un-used pin
|
|
* OC4
|
|
*/
|
|
{ 1, 4, 0x0040 }, /* P8= Camera (no OC) */
|
|
{ 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
|
|
{ 0, 4, 0x0000 }, /* P10= Empty */
|
|
{ 0, 4, 0x0000 }, /* P11= Empty */
|
|
{ 0, 4, 0x0000 }, /* P12= Empty */
|
|
{ 0, 4, 0x0000 }, /* P13= Empty */
|
|
},
|
|
};
|
|
pci_dev_t dev = PCI_BDF(0, 0, 0);
|
|
int ret;
|
|
|
|
debug("Boot mode %d\n", gd->arch.pei_boot_mode);
|
|
debug("mcr_input %p\n", pei_data.mrc_input);
|
|
pei_data.boot_mode = gd->arch.pei_boot_mode;
|
|
ret = copy_spd(&pei_data);
|
|
if (!ret)
|
|
ret = sdram_initialise(&pei_data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
rcba_config();
|
|
quick_ram_check();
|
|
|
|
writew(0xCAFE, MCHBAR_REG(SSKPD));
|
|
|
|
post_code(POST_DRAM);
|
|
|
|
ret = sdram_find(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
gd->ram_size = gd->arch.meminfo.total_32bit_memory;
|
|
|
|
return 0;
|
|
}
|