mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 22:26:16 +09:00
b37f772433
This adds a first support of the FPGA download for a PCIe FPGA based on the BOCO2 CPLD. This takes place in 3 steps, all done accessing the SPICTRL reg of the BOCO2: 1) start the FPGA config with an access to the FPGA_PROG bit 2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1 for the end of the FPGA configuration (with a timeout) 3) reset the FPGA 4) finally remove the access to its config EEPROM from the FPGA so that the CPU can update the FPGA configuration when the kernel is running The boards with a PCIe FPGA but without BOCO2 still are supported. The config option name is CONFIG_KM_FPGA_CONFIG Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
156 lines
3.0 KiB
C
156 lines
3.0 KiB
C
/*
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* (C) Copyright 2008
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __KEYMILE_COMMON_H
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#define __KEYMILE_COMMON_H
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#define WRG_RESET 0x80
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#define H_OPORTS_14 0x40
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#define WRG_LED 0x02
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#define WRL_BOOT 0x01
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#define OPRTL_XBUFENA 0x20
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#define H_OPORTS_SCC4_ENA 0x10
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#define H_OPORTS_SCC4_FD_ENA 0x04
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#define H_OPORTS_FCC1_PW_DWN 0x01
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#define PIGGY_PRESENT 0x80
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struct km_bec_fpga {
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unsigned char id;
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unsigned char rev;
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unsigned char oprth;
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unsigned char oprtl;
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unsigned char res1[3];
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unsigned char bprth;
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unsigned char bprtl;
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unsigned char gprt3;
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unsigned char gprt2;
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unsigned char gprt1;
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unsigned char gprt0;
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unsigned char res2[2];
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unsigned char prst;
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unsigned char res3[0xfff0];
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unsigned char pgy_id;
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unsigned char pgy_rev;
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unsigned char pgy_outputs;
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unsigned char pgy_eth;
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};
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#define BFTICU_DIPSWITCH_MASK 0x0f
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/*
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* BFTICU FPGA iomap
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* BFTICU is used on mgcoge and mgocge3ne
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*/
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struct bfticu_iomap {
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u8 xi_ena; /* General defect enable */
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u8 pack1[3];
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u8 en_csn;
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u8 pack2;
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u8 safe_mem;
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u8 pack3;
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u8 id;
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u8 pack4;
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u8 rev;
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u8 build;
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u8 p_frc;
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u8 p_msk;
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u8 pack5[2];
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u8 xg_int;
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u8 pack6[15];
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u8 s_conf;
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u8 pack7;
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u8 dmx_conf12;
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u8 pack8;
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u8 s_clkslv;
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u8 pack9[11];
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u8 d_conf;
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u8 d_mask_ca;
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u8 d_pll_del;
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u8 pack10[16];
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u8 t_conf_ca;
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u8 t_mask_ca;
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u8 pack11[13];
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u8 m_def0;
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u8 m_def1;
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u8 m_def2;
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u8 m_def3;
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u8 m_def4;
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u8 m_def5;
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u8 m_def_trap0;
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u8 m_def_trap1;
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u8 m_def_trap2;
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u8 m_def_trap3;
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u8 m_def_trap4;
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u8 m_def_trap5;
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u8 m_mask_def0;
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u8 m_mask_def1;
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u8 m_mask_def2;
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u8 m_mask_def3;
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u8 m_mask_def4;
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u8 m_mask_def5;
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u8 m_def_mask0;
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u8 m_def_mask1;
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u8 m_def_mask2;
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u8 m_def_mask3;
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u8 m_def_mask4;
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u8 m_def_mask5;
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u8 m_def_pri;
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u8 pack12[11];
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u8 hw_status;
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u8 pack13;
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u8 hw_control1;
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u8 hw_control2;
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u8 hw_control3;
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u8 pack14[7];
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u8 led_on; /* Leds */
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u8 pack15;
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u8 sfp_control; /* SFP modules */
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u8 pack16;
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u8 alarm_control; /* Alarm output */
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u8 pack17;
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u8 icps; /* ICN clock pulse shaping */
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u8 mswitch; /* Read mode switch */
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u8 pack18[6];
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u8 pb_dbug;
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};
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#if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
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#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0
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#endif
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int ethernet_present(void);
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int ivm_read_eeprom(void);
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int trigger_fpga_config(void);
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int wait_for_fpga_config(void);
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int fpga_reset(void);
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int toggle_eeprom_spi_bus(void);
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int set_km_env(void);
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int fdt_set_node_and_value(void *blob,
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char *nodename,
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char *regname,
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void *var,
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int size);
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int fdt_get_node_and_value(void *blob,
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char *nodename,
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char *propname,
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void **var);
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#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
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#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
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int i2c_soft_read_pin(void);
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int i2c_make_abort(void);
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#endif /* __KEYMILE_COMMON_H */
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