mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-12 13:13:44 +09:00
168a5acb81
This reverts commit 0e57968a21.
The short version of the original commit is that some i2c devices cannot
be probed via read as they NAK the first cycle, so try and probe via a
write that we abort before it writes to the device. This however is not
allowed by the TRM for any of these parts. The section on I2C_CON
(table 17-35 I2C_CON for am/dm37x for example) says you must not change
the register while STT has been set. On these parts, the unpredictable
behavior that the chip exhibits is not problematic. On OMAP4 however it
results in the chip being in a bad state:
Panda # i2c probe
Valid chip addresses: 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A
2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42
43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A
5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72
73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
Panda # i2c md 50 0
timed out in wait_for_pin: I2C_STAT=0
I2C read: I/O error
Error reading the chip.
We must revert the original behavior to bring probe back into line with
the TRM.
Cc: Nick Thompson <nick.thompson@ge.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
473 lines
11 KiB
C
473 lines
11 KiB
C
/*
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* Basic I2C functions
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*
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* Copyright (c) 2004 Texas Instruments
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*
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* This package is free software; you can redistribute it and/or
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* modify it under the terms of the license found in the file
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* named COPYING that should have accompanied this file.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Author: Jian Zhang jzhang@ti.com, Texas Instruments
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*
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* Copyright (c) 2003 Wolfgang Denk, wd@denx.de
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* Rewritten to fit into the current U-Boot framework
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*
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* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
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*
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*/
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#include <common.h>
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#include <asm/arch/i2c.h>
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#include <asm/io.h>
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#include "omap24xx_i2c.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define I2C_TIMEOUT 1000
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static void wait_for_bb(void);
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static u16 wait_for_pin(void);
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static void flush_fifo(void);
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/*
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* For SPL boot some boards need i2c before SDRAM is initialised so force
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* variables to live in SRAM
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*/
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static struct i2c __attribute__((section (".data"))) *i2c_base =
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(struct i2c *)I2C_DEFAULT_BASE;
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static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
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{ [0 ... (I2C_BUS_MAX-1)] = 0 };
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static unsigned int __attribute__((section (".data"))) current_bus = 0;
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void i2c_init(int speed, int slaveadd)
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{
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int psc, fsscll, fssclh;
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int hsscll = 0, hssclh = 0;
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u32 scll, sclh;
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int timeout = I2C_TIMEOUT;
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/* Only handle standard, fast and high speeds */
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if ((speed != OMAP_I2C_STANDARD) &&
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(speed != OMAP_I2C_FAST_MODE) &&
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(speed != OMAP_I2C_HIGH_SPEED)) {
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printf("Error : I2C unsupported speed %d\n", speed);
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return;
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}
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psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
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psc -= 1;
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if (psc < I2C_PSC_MIN) {
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printf("Error : I2C unsupported prescalar %d\n", psc);
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return;
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}
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if (speed == OMAP_I2C_HIGH_SPEED) {
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/* High speed */
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/* For first phase of HS mode */
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fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
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(2 * OMAP_I2C_FAST_MODE);
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fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
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fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing first phase clock\n");
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return;
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}
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/* For second phase of HS mode */
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hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
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hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
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hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing second phase clock\n");
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return;
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}
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scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
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sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
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} else {
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/* Standard and fast speed */
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fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
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fsscll -= I2C_FASTSPEED_SCLL_TRIM;
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fssclh -= I2C_FASTSPEED_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing clock\n");
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return;
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}
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scll = (unsigned int)fsscll;
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sclh = (unsigned int)fssclh;
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}
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if (readw(&i2c_base->con) & I2C_CON_EN) {
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writew(0, &i2c_base->con);
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udelay(50000);
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}
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writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
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udelay(1000);
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writew(I2C_CON_EN, &i2c_base->con);
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while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
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if (timeout <= 0) {
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puts("ERROR: Timeout in soft-reset\n");
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return;
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}
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udelay(1000);
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}
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writew(0, &i2c_base->con);
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writew(psc, &i2c_base->psc);
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writew(scll, &i2c_base->scll);
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writew(sclh, &i2c_base->sclh);
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/* own address */
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writew(slaveadd, &i2c_base->oa);
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writew(I2C_CON_EN, &i2c_base->con);
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/* have to enable intrrupts or OMAP i2c module doesn't work */
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writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
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I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
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udelay(1000);
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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if (gd->flags & GD_FLG_RELOC)
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bus_initialized[current_bus] = 1;
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}
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static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
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{
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int i2c_error = 0;
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u16 status;
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/* wait until bus not busy */
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wait_for_bb();
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/* one byte only */
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writew(1, &i2c_base->cnt);
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/* set slave address */
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writew(devaddr, &i2c_base->sa);
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/* no stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
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I2C_CON_TRX, &i2c_base->con);
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/* send register offset */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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if (status & I2C_STAT_XRDY) {
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/* Important: have to use byte access */
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writeb(regoffset, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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/* set slave address */
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writew(devaddr, &i2c_base->sa);
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/* read one byte from slave */
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writew(1, &i2c_base->cnt);
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/* need stop bit here */
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writew(I2C_CON_EN | I2C_CON_MST |
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I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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/* receive data */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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if (status & I2C_STAT_RRDY) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX)
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*value = readb(&i2c_base->data);
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#else
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*value = readw(&i2c_base->data);
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#endif
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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read_exit:
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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return i2c_error;
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}
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static void flush_fifo(void)
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{ u16 stat;
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/* note: if you try and read data when its not there or ready
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* you get a bus error
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*/
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while (1) {
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stat = readw(&i2c_base->stat);
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if (stat == I2C_STAT_RRDY) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX)
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readb(&i2c_base->data);
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#else
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readw(&i2c_base->data);
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#endif
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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udelay(1000);
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} else
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break;
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}
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}
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int i2c_probe(uchar chip)
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{
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u16 status;
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int res = 1; /* default = fail */
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if (chip == readw(&i2c_base->oa))
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return res;
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/* wait until bus not busy */
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wait_for_bb();
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/* try to read one byte */
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writew(1, &i2c_base->cnt);
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/* set slave address */
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writew(chip, &i2c_base->sa);
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/* stop bit needed here */
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writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_AL) {
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res = 1;
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goto probe_exit;
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}
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if (status & I2C_STAT_NACK) {
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res = 1;
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writew(0xff, &i2c_base->stat);
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writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
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wait_for_bb ();
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break;
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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if (status & I2C_STAT_RRDY) {
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res = 0;
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX)
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readb(&i2c_base->data);
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#else
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readw(&i2c_base->data);
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#endif
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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}
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probe_exit:
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flush_fifo();
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/* don't allow any more data in... we don't want it. */
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writew(0, &i2c_base->cnt);
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writew(0xFFFF, &i2c_base->stat);
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return res;
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}
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int i;
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if (alen > 1) {
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printf("I2C read: addr len %d not supported\n", alen);
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return 1;
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}
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if (addr + len > 256) {
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puts("I2C read: address out of range\n");
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return 1;
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}
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for (i = 0; i < len; i++) {
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if (i2c_read_byte(chip, addr + i, &buffer[i])) {
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puts("I2C read: I/O error\n");
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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return 1;
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}
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}
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return 0;
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int i;
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u16 status;
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int i2c_error = 0;
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if (alen > 1) {
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printf("I2C write: addr len %d not supported\n", alen);
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return 1;
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}
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if (addr + len > 256) {
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printf("I2C write: address 0x%x + 0x%x out of range\n",
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addr, len);
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return 1;
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}
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/* wait until bus not busy */
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wait_for_bb();
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/* start address phase - will write regoffset + len bytes data */
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/* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
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writew(alen + len, &i2c_base->cnt);
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/* set slave address */
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writew(chip, &i2c_base->sa);
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/* stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con);
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/* Send address byte */
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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printf("error waiting for i2c address ACK (status=0x%x)\n",
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status);
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goto write_exit;
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}
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if (status & I2C_STAT_XRDY) {
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writeb(addr & 0xFF, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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} else {
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i2c_error = 1;
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printf("i2c bus not ready for transmit (status=0x%x)\n",
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status);
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goto write_exit;
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}
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/* address phase is over, now write data */
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for (i = 0; i < len; i++) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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printf("i2c error waiting for data ACK (status=0x%x)\n",
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status);
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goto write_exit;
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}
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if (status & I2C_STAT_XRDY) {
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writeb(buffer[i], &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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} else {
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i2c_error = 1;
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printf("i2c bus not ready for Tx (i=%d)\n", i);
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goto write_exit;
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}
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}
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write_exit:
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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return i2c_error;
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}
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static void wait_for_bb(void)
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{
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int timeout = I2C_TIMEOUT;
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u16 stat;
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writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
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while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
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writew(stat, &i2c_base->stat);
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udelay(1000);
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}
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if (timeout <= 0) {
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printf("timed out in wait_for_bb: I2C_STAT=%x\n",
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readw(&i2c_base->stat));
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}
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writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
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}
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static u16 wait_for_pin(void)
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{
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u16 status;
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int timeout = I2C_TIMEOUT;
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do {
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udelay(1000);
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status = readw(&i2c_base->stat);
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} while (!(status &
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(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
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I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
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I2C_STAT_AL)) && timeout--);
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if (timeout <= 0) {
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printf("timed out in wait_for_pin: I2C_STAT=%x\n",
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readw(&i2c_base->stat));
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writew(0xFFFF, &i2c_base->stat);
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status = 0;
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}
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return status;
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}
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int i2c_set_bus_num(unsigned int bus)
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{
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if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
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printf("Bad bus: %d\n", bus);
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return -1;
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}
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#if I2C_BUS_MAX == 3
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if (bus == 2)
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i2c_base = (struct i2c *)I2C_BASE3;
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else
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#endif
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if (bus == 1)
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i2c_base = (struct i2c *)I2C_BASE2;
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else
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i2c_base = (struct i2c *)I2C_BASE1;
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|
|
current_bus = bus;
|
|
|
|
if (!bus_initialized[current_bus])
|
|
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i2c_get_bus_num(void)
|
|
{
|
|
return (int) current_bus;
|
|
}
|