mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
87 lines
3.2 KiB
C
87 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2014 Google Inc.
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*
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* This file is from coreboot soc/intel/broadwell/include/soc/spi.h
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*/
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#ifndef _BROADWELL_SPI_H_
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#define _BROADWELL_SPI_H_
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/*
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* SPI Opcode Menu setup for SPIBAR lockdown
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* should support most common flash chips.
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*/
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#define SPIBAR_OFFSET 0x3800
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#define SPI_REG(x) (RCB_REG(SPIBAR_OFFSET + (x)))
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/* Reigsters within the SPIBAR */
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#define SPIBAR_SSFC 0x91
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#define SPIBAR_FDOC 0xb0
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#define SPIBAR_FDOD 0xb4
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#define SPIBAR_PREOP 0x94
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#define SPIBAR_OPTYPE 0x96
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#define SPIBAR_OPMENU_LOWER 0x98
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#define SPIBAR_OPMENU_UPPER 0x9c
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#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
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#define SPI_OPTYPE_0 0x01 /* Write, no address */
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#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
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#define SPI_OPTYPE_1 0x03 /* Write, address required */
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#define SPI_OPMENU_2 0x03 /* READ: Read Data */
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#define SPI_OPTYPE_2 0x02 /* Read, address required */
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#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
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#define SPI_OPTYPE_3 0x00 /* Read, no address */
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#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
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#define SPI_OPTYPE_4 0x03 /* Write, address required */
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#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
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#define SPI_OPTYPE_5 0x00 /* Read, no address */
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#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
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#define SPI_OPTYPE_6 0x03 /* Write, address required */
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#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
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#define SPI_OPTYPE_7 0x02 /* Read, address required */
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#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
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(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
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#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
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(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
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#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
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(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
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(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
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(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
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#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
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#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
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#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
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#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
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#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
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#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
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#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
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#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
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#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
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#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
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#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
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#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
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#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
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#define SPIBAR_FADDR 0x08 /* SPI flash address */
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#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
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#define SPIBAR_SSFS 0x90
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#define SPIBAR_SSFS_ERROR (1 << 3)
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#define SPIBAR_SSFS_DONE (1 << 2)
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#define SPIBAR_SSFC 0x91
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#define SPIBAR_SSFC_DATA (1 << 14)
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#define SPIBAR_SSFC_GO (1 << 1)
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#endif
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