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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
264 lines
5.6 KiB
C
264 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright 2016-2019 NXP Semiconductors
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <fdt_support.h>
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#include <init.h>
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#include <asm/arch-ls102xa/ls102xa_soc.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/fsl_serdes.h>
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#include "../common/sleep.h"
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#include <fsl_validate.h>
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#include <fsl_immap.h>
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#include <fsl_csu.h>
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#include <netdev.h>
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#include <spl.h>
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#ifdef CONFIG_U_QE
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#include <fsl_qe.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static void ddrmc_init(void)
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{
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#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
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struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
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u32 temp_sdram_cfg, tmp;
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
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out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
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out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
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out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
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out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
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out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
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out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
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out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
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#ifdef CONFIG_DEEP_SLEEP
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if (is_warm_boot()) {
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out_be32(&ddr->sdram_cfg_2,
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DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
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out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
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out_be32(&ddr->init_ext_addr, (1 << 31));
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/* DRAM VRef will not be trained */
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out_be32(&ddr->ddr_cdr2,
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DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
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} else
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#endif
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{
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out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
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out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
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}
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out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
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out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
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out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
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out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
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out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
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out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
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out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
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out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
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out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
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/* DDR erratum A-009942 */
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tmp = in_be32(&ddr->debug[28]);
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out_be32(&ddr->debug[28], tmp | 0x0070006f);
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udelay(1);
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#ifdef CONFIG_DEEP_SLEEP
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if (is_warm_boot()) {
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/* enter self-refresh */
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temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
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temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
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out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
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temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
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} else
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#endif
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temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
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#ifdef CONFIG_DEEP_SLEEP
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if (is_warm_boot()) {
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/* exit self-refresh */
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temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
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temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
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out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
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}
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#endif
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#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
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}
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int dram_init(void)
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{
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ddrmc_init();
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erratum_a008850_post();
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
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fsl_dp_resume();
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#endif
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_TSEC_ENET
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/*
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* Clear BD & FR bits for big endian BD's and frame data (aka set
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* correct eTSEC endianness). This is crucial in ensuring that it does
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* not report Data Parity Errors in its RX/TX FIFOs when attempting to
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* send traffic.
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*/
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clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
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/* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
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#endif
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arch_soc_init();
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot()) {
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timer_init();
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dram_init();
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}
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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void (*second_uboot)(void);
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/* Clear the BSS */
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memset(__bss_start, 0, __bss_end - __bss_start);
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get_clocks();
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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preloader_console_init();
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dram_init();
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/* Allow OCRAM access permission as R/W */
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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enable_layerscape_ns_access();
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#endif
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/*
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* if it is woken up from deep sleep, then jump to second
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* stage U-Boot and continue executing without recopying
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* it from SD since it has already been reserved in memory
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* in last boot.
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*/
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if (is_warm_boot()) {
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second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
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second_uboot();
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}
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board_init_r(NULL, 0);
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}
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#endif
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int board_init(void)
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{
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#ifndef CONFIG_SYS_FSL_NO_SERDES
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fsl_serdes_init();
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#endif
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ls102xa_smmu_stream_id_init();
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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#ifdef CONFIG_U_QE
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u_qe_init();
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#endif
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return 0;
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}
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#if defined(CONFIG_SPL_BUILD)
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void spl_board_init(void)
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{
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ls102xa_smmu_stream_id_init();
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}
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#endif
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_CHAIN_OF_TRUST
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fsl_setenv_chain_of_trust();
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#endif
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return 0;
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}
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#endif
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#if defined(CONFIG_MISC_INIT_R)
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int misc_init_r(void)
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{
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#ifdef CONFIG_FSL_DEVICE_DISABLE
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device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
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#endif
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#ifdef CONFIG_FSL_CAAM
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return sec_init();
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#endif
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}
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#endif
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#if defined(CONFIG_DEEP_SLEEP)
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void board_sleep_prepare(void)
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{
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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}
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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