mirror of
https://github.com/brain-hackers/u-boot-brain
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656e6cc86b
Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
19 lines
538 B
Makefile
19 lines
538 B
Makefile
#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += pinctrl-uclass.o
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obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
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obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
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obj-y += nxp/
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obj-$(CONFIG_ARCH_ATH79) += ath79/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
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obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
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obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
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obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
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obj-$(CONFIG_PINCTRL_MESON) += meson/
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obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/
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