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https://github.com/brain-hackers/u-boot-brain
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b5867b1a7a
This patch adds a basic group of devicetrees, one for each cpu family, including actually just uart and dspi devices, since these are the drivers supporting devicetree (support added in this patch-set). Acked-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Angelo Dureghello <angelo@sysam.it> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
31 lines
922 B
Plaintext
31 lines
922 B
Plaintext
Freescale ColdFire DSPI controller
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Required properties:
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- compatible : "fsl,mcf-dspi"
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- #address-cells: <1>, as required by generic SPI binding
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- #size-cells: <0>, also as required by generic SPI binding
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- reg : offset and length of the register set for the device
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Optional properties:
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- spi-max-frequency : max supported spi frequency
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- num-cs : the number of the chipselect signals
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- spi-mode: spi motorola mode, 0 to 3
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- ctar-params: CTAR0 to 7 register configuration, as an array
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of 8 integer fields for each register, where each register
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is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
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Example:
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dspi0: dspi@fc05c000 {
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compatible = "fsl,mcf-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfc05c000 0x100>;
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spi-max-frequency = <50000000>;
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num-cs = <4>;
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spi-mode = <0>;
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ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>,
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<7, 0, 0, 0, 0, 0, 1, 6>,
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<7, 0, 0, 0, 0, 0, 1, 6>;
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};
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