mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
435acd83b2
Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
35 lines
560 B
C
35 lines
560 B
C
/*
|
|
* Copyright 2015 Freescale Semiconductor
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*
|
|
*/
|
|
|
|
#ifndef __FSL_CSU_H__
|
|
#define __FSL_CSU_H__
|
|
|
|
enum csu_cslx_access {
|
|
CSU_NS_SUP_R = 0x08,
|
|
CSU_NS_SUP_W = 0x80,
|
|
CSU_NS_SUP_RW = 0x88,
|
|
CSU_NS_USER_R = 0x04,
|
|
CSU_NS_USER_W = 0x40,
|
|
CSU_NS_USER_RW = 0x44,
|
|
CSU_S_SUP_R = 0x02,
|
|
CSU_S_SUP_W = 0x20,
|
|
CSU_S_SUP_RW = 0x22,
|
|
CSU_S_USER_R = 0x01,
|
|
CSU_S_USER_W = 0x10,
|
|
CSU_S_USER_RW = 0x11,
|
|
CSU_ALL_RW = 0xff,
|
|
};
|
|
|
|
struct csu_ns_dev {
|
|
unsigned long ind;
|
|
uint32_t val;
|
|
};
|
|
|
|
void enable_layerscape_ns_access(void);
|
|
|
|
#endif
|