Ashish Kumar 63b2316c5c fsl-layerscape: Consolidate registers space defination for CCI-400 bus ... CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>		2017-09-11 07:55:36 -07:00
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asm	fsl-layerscape: Consolidate registers space defination for CCI-400 bus	2017-09-11 07:55:36 -07:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00