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![Horatiu Vultur](/assets/img/avatar_default.png)
Update device tree for ocelot to add support for ocelot pcb120. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
246 lines
5.1 KiB
Plaintext
246 lines
5.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,ocelot";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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clocks = <&cpu_clk>;
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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cpuintc: interrupt-controller@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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cpu_clk: cpu-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <500000000>;
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};
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sys_clk: sys-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x70000000 0x2000000>;
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interrupt-parent = <&intc>;
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cpu_ctrl: syscon@0 {
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compatible = "mscc,ocelot-cpu-syscon", "syscon";
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reg = <0x0 0x2c>;
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};
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intc: interrupt-controller@70 {
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compatible = "mscc,ocelot-icpu-intr";
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reg = <0x70 0x70>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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uart0: serial@100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100000 0x20>;
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interrupts = <6>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100800 0x20>;
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interrupts = <7>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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spi0: spi-master@101000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-ssi";
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reg = <0x101000 0x40>;
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num-chipselect = <4>;
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bus-num = <0>;
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reg-io-width = <4>;
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reg-shift = <2>;
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spi-max-frequency = <18000000>; /* input clock */
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clocks = <&ahb_clk>;
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status = "disabled";
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};
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switch: switch@1010000 {
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pinctrl-0 = <&miim1_pins>;
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pinctrl-names = "default";
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compatible = "mscc,vsc7514-switch";
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reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0
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<0x11f0000 0x100>, // VTSS_TO_DEV_1
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<0x1200000 0x100>, // VTSS_TO_DEV_2
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<0x1210000 0x100>, // VTSS_TO_DEV_3
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<0x1220000 0x100>, // VTSS_TO_DEV_4
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<0x1230000 0x100>, // VTSS_TO_DEV_5
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<0x1240000 0x100>, // VTSS_TO_DEV_6
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<0x1250000 0x100>, // VTSS_TO_DEV_7
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<0x1260000 0x100>, // VTSS_TO_DEV_8
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<0x1270000 0x100>, // VTSS_TO_DEV_9
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<0x1280000 0x100>, // VTSS_TO_DEV_10
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<0x1010000 0x10000>, // VTSS_TO_SYS
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<0x1030000 0x10000>, // VTSS_TO_REW
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<0x1080000 0x100>, // VTSS_TO_DEVCPU_QS
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<0x10d0000 0x10000>, // VTSS_TO_HSIO
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<0x1800000 0x80000>,// VTSS_TO_QSYS
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<0x1880000 0x10000>;// VTSS_TO_ANA
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reg-names = "port0", "port1", "port2", "port3", "port4",
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"port5", "port6", "port7", "port8", "port9",
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"port10",
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"sys", "rew", "qs", "hsio", "qsys", "ana";
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interrupts = <21 22>;
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interrupt-names = "xtr", "inj";
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status = "okay";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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mdio0: mdio@107009c {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,ocelot-miim";
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reg = <0x107009c 0x24>;
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interrupts = <14>;
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status = "disabled";
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};
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mdio1: mdio@10700f0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,ocelot-miim";
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reg = <0x10700c0 0x24>;
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interrupts = <14>;
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status = "disabled";
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};
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hsio: syscon@10d0000 {
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compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
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reg = <0x10d0000 0x10000>;
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serdes_hsio: serdes_hsio {
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compatible = "mscc,vsc7514-serdes";
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#phy-cells = <3>;
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};
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};
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reset@1070008 {
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compatible = "mscc,ocelot-chip-reset";
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reg = <0x1070008 0x4>;
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};
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gpio: pinctrl@1070034 {
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compatible = "mscc,ocelot-pinctrl";
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reg = <0x1070034 0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 22>;
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sgpio_pins: sgpio-pins {
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pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
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function = "sg0";
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};
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uart_pins: uart-pins {
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pins = "GPIO_6", "GPIO_7";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_12", "GPIO_13";
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function = "uart2";
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};
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spi_cs1_pin: spi-cs1-pin {
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pins = "GPIO_8";
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function = "si";
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};
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miim1_pins: miim1-pins {
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pins = "GPIO_14", "GPIO_15";
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function = "miim1";
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};
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spi_cs2_pin: spi-cs2-pin {
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pins = "GPIO_9";
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function = "si";
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};
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spi_cs3_pin: spi-cs3-pin {
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pins = "GPIO_16";
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function = "si";
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};
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spi_cs4_pin: spi-cs4-pin {
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pins = "GPIO_17";
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function = "si";
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};
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};
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sgpio: gpio@10700f8 {
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compatible = "mscc,ocelot-sgpio";
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status = "disabled";
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clocks = <&sys_clk>;
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pinctrl-0 = <&sgpio_pins>;
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pinctrl-names = "default";
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reg = <0x10700f8 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio 0 0 64>;
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};
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};
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};
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