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https://github.com/brain-hackers/u-boot-brain
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![Michal Simek](/assets/img/avatar_default.png)
Just sync between version. Others zynqmp boards have this setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
235 lines
4.0 KiB
Plaintext
235 lines
4.0 KiB
Plaintext
/*
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* dts file for Xilinx ZynqMP ep108 development board
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*
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* (C) Copyright 2014 - 2015, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-ep108-clk.dtsi"
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/ {
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model = "ZynqMP EP108";
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aliases {
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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serial0 = &uart0;
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spi0 = &qspi;
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spi1 = &spi0;
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spi2 = &spi1;
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usb0 = &usb0;
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usb1 = &usb1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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};
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&can0 {
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status = "okay";
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};
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&can1 {
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status = "okay";
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};
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&gem0 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: phy@0 {
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reg = <0>;
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max-speed = <100>;
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};
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};
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&gpio {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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eeprom@54 {
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compatible = "at,24c64";
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reg = <0x54>;
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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eeprom@55 {
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compatible = "at,24c64";
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reg = <0x55>;
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};
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};
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&nand0 {
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status = "okay";
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arasan,has-mdma;
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num-cs = <1>;
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partition@0 { /* for testing purpose */
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label = "nand-fsbl-uboot";
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reg = <0x0 0x0 0x400000>;
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};
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partition@1 { /* for testing purpose */
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label = "nand-linux";
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reg = <0x0 0x400000 0x1400000>;
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};
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partition@2 { /* for testing purpose */
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label = "nand-device-tree";
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reg = <0x0 0x1800000 0x400000>;
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};
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partition@3 { /* for testing purpose */
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label = "nand-rootfs";
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reg = <0x0 0x1C00000 0x1400000>;
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};
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partition@4 { /* for testing purpose */
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label = "nand-bitstream";
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reg = <0x0 0x3000000 0x400000>;
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};
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partition@5 { /* for testing purpose */
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label = "nand-misc";
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reg = <0x0 0x3400000 0xFCC00000>;
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};
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <10000000>;
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partition@qspi-fsbl-uboot { /* for testing purpose */
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@qspi-linux { /* for testing purpose */
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@qspi-device-tree { /* for testing purpose */
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@qspi-rootfs { /* for testing purpose */
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label = "qspi-rootfs";
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reg = <0x620000 0x5E0000>;
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};
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};
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};
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&sata {
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status = "okay";
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ceva,broken-gen2;
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/* SATA Phy OOB timing settings */
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ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
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ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
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ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
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ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
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ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
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ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
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ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
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};
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&sdhci0 {
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status = "okay";
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bus-width = <8>;
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xlnx,mio_bank = <2>;
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};
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&sdhci1 {
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status = "okay";
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xlnx,mio_bank = <1>;
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};
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&spi0 {
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status = "okay";
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num-cs = <1>;
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spi0_flash0: spi0_flash0@0 {
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compatible = "m25p80";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi0_flash0@00000000 {
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label = "spi0_flash0";
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reg = <0x0 0x100000>;
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};
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};
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};
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&spi1 {
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status = "okay";
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num-cs = <1>;
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spi1_flash0: spi1_flash0@0 {
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compatible = "m25p80";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi1_flash0@00000000 {
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label = "spi1_flash0";
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reg = <0x0 0x100000>;
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "peripheral";
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maximum-speed = "high-speed";
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};
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&usb1 {
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status = "okay";
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};
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&dwc3_1 {
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status = "okay";
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dr_mode = "host";
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maximum-speed = "high-speed";
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};
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&watchdog0 {
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status = "okay";
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};
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&xlnx_dp {
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xlnx,max-pclock-frequency = <200000>;
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};
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&xlnx_dpdma {
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xlnx,axi-clock-freq = <200000000>;
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};
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