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ba94a1bba3
- Add IXP4xx NPE ethernet MAC support - Add support for Intel IXDPG425 board - Add support for Prodrive PDNB3 board - Add IRQ support Patch by Stefan Roese, 23 May 2006 [This patch does not include cpu/ixp/npe/IxNpeMicrocode.c which still sufferes from licensing issues. Blame Intel.]
410 lines
12 KiB
C
410 lines
12 KiB
C
/**
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* @file IxAtmTypes.h
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*
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* @date 24-MAR-2002
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*
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* @brief This file contains Atm types common to a number of Atm components.
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/* ------------------------------------------------------
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Doxygen group definitions
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------------------------------------------------------ */
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/**
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* @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes)
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*
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* @brief The common set of types used in many Atm components
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*
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* @{ */
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#ifndef IXATMTYPES_H
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#define IXATMTYPES_H
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#include "IxNpeA.h"
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/**
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* @enum IxAtmLogicalPort
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*
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* @brief Logical Port Definitions :
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*
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* Only 1 port is available in SPHY configuration
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* 12 ports are enabled in MPHY configuration
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*
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*/
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typedef enum
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{
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IX_UTOPIA_PORT_0 = 0, /**< Port 0 */
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#ifdef IX_NPE_MPHYMULTIPORT
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IX_UTOPIA_PORT_1, /**< Port 1 */
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IX_UTOPIA_PORT_2, /**< Port 2 */
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IX_UTOPIA_PORT_3, /**< Port 3 */
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IX_UTOPIA_PORT_4, /**< Port 4 */
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IX_UTOPIA_PORT_5, /**< Port 5 */
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IX_UTOPIA_PORT_6, /**< Port 6 */
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IX_UTOPIA_PORT_7, /**< Port 7 */
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IX_UTOPIA_PORT_8, /**< Port 8 */
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IX_UTOPIA_PORT_9, /**< Port 9 */
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IX_UTOPIA_PORT_10, /**< Port 10 */
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IX_UTOPIA_PORT_11, /**< Port 11 */
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#endif /* IX_NPE_MPHY */
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IX_UTOPIA_MAX_PORTS /**< Not a port - just a definition for the
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* maximum possible ports
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*/
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} IxAtmLogicalPort;
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/**
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* @def IX_ATM_CELL_PAYLOAD_SIZE
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* @brief Size of a ATM cell payload
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*/
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#define IX_ATM_CELL_PAYLOAD_SIZE (48)
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/**
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* @def IX_ATM_CELL_SIZE
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* @brief Size of a ATM cell, including header
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*/
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#define IX_ATM_CELL_SIZE (53)
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/**
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* @def IX_ATM_CELL_SIZE_NO_HEC
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* @brief Size of a ATM cell, excluding HEC byte
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*/
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#define IX_ATM_CELL_SIZE_NO_HEC (IX_ATM_CELL_SIZE - 1)
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/**
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* @def IX_ATM_OAM_CELL_SIZE_NO_HEC
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* @brief Size of a OAM cell, excluding HEC byte
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*/
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#define IX_ATM_OAM_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC
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/**
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* @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE
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* @brief Size of a AAL0 48 Cell payload
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*/
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#define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE
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/**
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* @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE
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* @brief Size of a AAL5 Cell payload
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*/
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#define IX_ATM_AAL5_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE
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/**
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* @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC
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* @brief Size of a AAL0 52 Cell, excluding HEC byte
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*/
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#define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC
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/**
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* @def IX_ATM_MAX_VPI
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* @brief Maximum value of an ATM VPI
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*/
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#define IX_ATM_MAX_VPI 255
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/**
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* @def IX_ATM_MAX_VCI
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* @brief Maximum value of an ATM VCI
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*/
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#define IX_ATM_MAX_VCI 65535
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/**
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* @def IX_ATM_MAX_NUM_AAL_VCS
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* @brief Maximum number of active AAL5/AAL0 VCs in the system
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*/
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#define IX_ATM_MAX_NUM_AAL_VCS 32
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/**
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* @def IX_ATM_MAX_NUM_VC
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* @brief Maximum number of active AAL5/AAL0 VCs in the system
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* The use of this macro is depreciated, it is retained for
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* backward compatiblity. For current software release
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* and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used.
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*/
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#define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS
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/**
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* @def IX_ATM_MAX_NUM_OAM_TX_VCS
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* @brief Maximum number of active OAM Tx VCs in the system,
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* 1 OAM VC per port
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*/
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#define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS
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/**
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* @def IX_ATM_MAX_NUM_OAM_RX_VCS
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* @brief Maximum number of active OAM Rx VCs in the system,
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* 1 OAM VC shared accross all ports
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*/
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#define IX_ATM_MAX_NUM_OAM_RX_VCS 1
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/**
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* @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS
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* @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system
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*/
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#define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS)
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/**
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* @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS
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* @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system
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*/
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#define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS)
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/**
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* @def IX_ATM_IDLE_CELLS_CONNID
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* @brief VC Id used to indicate idle cells in the returned schedule table.
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*/
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#define IX_ATM_IDLE_CELLS_CONNID 0
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/**
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* @def IX_ATM_CELL_HEADER_VCI_GET
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* @brief get the VCI field from a cell header
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*/
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#define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \
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(((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK);
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/**
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* @def IX_ATM_CELL_HEADER_VPI_GET
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* @brief get the VPI field from a cell header
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*/
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#define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \
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(((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK);
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/**
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* @def IX_ATM_CELL_HEADER_PTI_GET
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* @brief get the PTI field from a cell header
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*/
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#define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \
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((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK;
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/**
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* @typedef IxAtmCellHeader
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*
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* @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A
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*/
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typedef unsigned int IxAtmCellHeader;
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/**
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* @enum IxAtmServiceCategory
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*
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* @brief Enumerated type representing available ATM service categories.
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* For more informatoin on these categories, see "Traffic Management
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* Specification" v4.1, published by the ATM Forum -
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* http://www.atmforum.com
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*/
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typedef enum
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{
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IX_ATM_CBR, /**< Constant Bit Rate */
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IX_ATM_RTVBR, /**< Real Time Variable Bit Rate */
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IX_ATM_VBR, /**< Variable Bit Rate */
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IX_ATM_UBR, /**< Unspecified Bit Rate */
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IX_ATM_ABR /**< Available Bit Rate (not supported) */
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} IxAtmServiceCategory;
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/**
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*
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* @enum IxAtmRxQueueId
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*
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* @brief Rx Queue Type for RX traffic
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*
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* IxAtmRxQueueId defines the queues involved for receiving data.
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*
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* There are two queues to facilitate prioritisation handling
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* and processing the 2 queues with different algorithms and
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* constraints
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*
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* e.g. : one queue can carry voice (or time-critical traffic), the
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* other queue can carry non-voice traffic
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*
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*/
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typedef enum
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{
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IX_ATM_RX_A = 0, /**< RX queue A */
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IX_ATM_RX_B, /**< RX queue B */
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IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */
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} IxAtmRxQueueId;
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/**
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* @brief Structure describing an ATM traffic contract for a Virtual
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* Connection (VC).
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*
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* Structure is used to specify the requested traffic contract for a
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* VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup
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* interface.
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*
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* These parameters are defined by the ATM forum working group
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* (http://www.atmforum.com).
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*
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* @note Typical values for a voice channel 64 Kbit/s
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* - atmService @a IX_ATM_RTVBR
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* - pcr 400 (include IP overhead, and AAL5 trailer)
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* - cdvt 5000000 (5 ms)
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* - scr = pcr
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*
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* @note Typical values for a data channel 800 Kbit/s
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* - atmService @a IX_ATM_UBR
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* - pcr 1962 (include IP overhead, and AAL5 trailer)
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* - cdvt 5000000 (5 ms)
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*
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*/
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typedef struct
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{
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IxAtmServiceCategory atmService; /**< ATM service category */
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unsigned pcr; /**< Peak Cell Rate - cells per second */
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unsigned cdvt; /**< Cell Delay Variation Tolerance - in nanoseconds */
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unsigned scr; /**< Sustained Cell Rate - cells per second */
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unsigned mbs; /**< Max Burst Size - cells */
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unsigned mcr; /**< Minimum Cell Rate - cells per second */
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unsigned mfs; /**< Max Frame Size - cells */
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} IxAtmTrafficDescriptor;
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/**
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* @typedef IxAtmConnId
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*
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* @brief ATM VC data connection identifier.
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*
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* This is is generated by IxAtmdAcc when a successful connection is
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* made on a VC. The is the ID by which IxAtmdAcc knows an active
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* VC and should be used in IxAtmdAcc API calls to reference a
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* specific VC.
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*/
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typedef unsigned int IxAtmConnId;
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/**
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* @typedef IxAtmSchedulerVcId
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*
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* @brief ATM VC scheduling connection identifier.
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*
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* This id is generated and used by ATM Tx controller, generally
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* the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component
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* will request one of these Ids whenever a data connection on
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* a Tx VC is requested. This ID will be used in callbacks to
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* the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a
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* particular VC.
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*/
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typedef int IxAtmSchedulerVcId;
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/**
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* @typedef IxAtmNpeRxVcId
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*
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* @brief ATM Rx VC identifier used by the ATM Npe.
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*
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* This Id is generated by IxAtmdAcc when a successful data connection
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* is made on a rx VC.
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*/
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typedef unsigned int IxAtmNpeRxVcId;
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/**
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* @brief ATM Schedule Table entry
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*
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* This IxAtmScheduleTableEntry is used by an ATM scheduler to inform
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* IxAtmdAcc about the data to transmit (in term of cells per VC)
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*
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* This structure defines
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* @li the number of cells to be transmitted (numberOfCells)
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* @li the VC connection to be used for transmission (connId).
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*
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* @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the
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* corresponding number of idle cells will be transmitted to the hardware.
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*
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*/
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typedef struct
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{
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IxAtmConnId connId; /**< connection Id
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*
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* Identifier of VC from which cells are to be transmitted.
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* When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates
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* that the system should transmit the specified number
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* of idle cells. Unknown connIds result in the transmission
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* idle cells.
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*/
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unsigned int numberOfCells; /**< number of cells to transmit
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*
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* The number of contiguous cells to schedule from this VC
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* at this point. The valid range is from 1 to
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* @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This
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* number can swap over mbufs and pdus. OverSchduling results
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* in the transmission of idle cells.
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*/
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} IxAtmScheduleTableEntry;
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/**
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* @brief This structure defines a schedule table which gives details
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* on which data (from which VCs) should be transmitted for a
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* forthcoming period of time for a particular port and the
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* order in which that data should be transmitted.
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*
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* The schedule table consists of a series of entries each of which
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* will schedule one or more cells from a particular registered VC.
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* The total number of cells scheduled and the total number of
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* entries in the table are also indicated.
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*
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*/
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typedef struct
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{
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unsigned tableSize; /**< Number of entries
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*
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* Indicates the total number of
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* entries in the table.
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*/
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unsigned totalCellSlots; /**< Number of cells
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*
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* Indicates the total number of ATM
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* cells which are scheduled by all the
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* entries in the table.
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*/
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IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries
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*
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* Pointer to an array
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* containing tableSize entries
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*/
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} IxAtmScheduleTable;
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#endif /* IXATMTYPES_H */
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/**
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* @} defgroup IxAtmTypes
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*/
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