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https://github.com/brain-hackers/u-boot-brain
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![Marek Vasut](/assets/img/avatar_default.png)
On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes lead to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
236 lines
5.1 KiB
C
236 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Panasonic Corporation
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/unaligned.h>
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#include <linux/mtd/rawnand.h>
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#include "denali.h"
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#define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
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#define DENALI_MAP10 (2 << 26) /* high-level control plane */
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#define INDEX_CTRL_REG 0x0
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#define INDEX_DATA_REG 0x10
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#define SPARE_ACCESS 0x41
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#define MAIN_ACCESS 0x42
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#define PIPELINE_ACCESS 0x2000
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#define BANK(x) ((x) << 24)
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static void __iomem *denali_flash_mem =
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(void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
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static void __iomem *denali_flash_reg =
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(void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
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static const int flash_bank;
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static int page_size, oob_size, pages_per_block;
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static void index_addr(uint32_t address, uint32_t data)
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{
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writel(address, denali_flash_mem + INDEX_CTRL_REG);
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writel(data, denali_flash_mem + INDEX_DATA_REG);
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}
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static int wait_for_irq(uint32_t irq_mask)
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{
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unsigned long timeout = 1000000;
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uint32_t intr_status;
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do {
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intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
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if (intr_status & INTR__ECC_UNCOR_ERR) {
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debug("Uncorrected ECC detected\n");
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return -EBADMSG;
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}
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if (intr_status & irq_mask)
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break;
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udelay(1);
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timeout--;
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} while (timeout);
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if (!timeout) {
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debug("Timeout with interrupt status %08x\n", intr_status);
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return -EIO;
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}
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return 0;
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}
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static void read_data_from_flash_mem(uint8_t *buf, int len)
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{
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int i;
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uint32_t *buf32;
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/* transfer the data from the flash */
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buf32 = (uint32_t *)buf;
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/*
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* Let's take care of unaligned access although it rarely happens.
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* Avoid put_unaligned() for the normal use cases since it leads to
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* a bit performance regression.
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*/
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if ((unsigned long)buf32 % 4) {
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for (i = 0; i < len / 4; i++)
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put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG),
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buf32++);
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} else {
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for (i = 0; i < len / 4; i++)
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*buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
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}
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if (len % 4) {
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u32 tmp;
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tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG));
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buf = (uint8_t *)buf32;
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for (i = 0; i < len % 4; i++) {
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*buf++ = tmp;
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tmp >>= 8;
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}
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}
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}
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int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
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{
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uint32_t addr, cmd;
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static uint32_t page_count = 1;
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writel(ecc_en, denali_flash_reg + ECC_ENABLE);
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/* clear all bits of intr_status. */
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writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank));
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addr = BANK(flash_bank) | page;
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/* setup the acccess type */
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cmd = DENALI_MAP10 | addr;
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index_addr(cmd, access_type);
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/* setup the pipeline command */
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index_addr(cmd, PIPELINE_ACCESS | page_count);
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cmd = DENALI_MAP01 | addr;
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writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
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return wait_for_irq(INTR__LOAD_COMP);
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}
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static int nand_read_oob(void *buf, int page)
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{
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int ret;
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ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS);
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if (ret < 0)
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return ret;
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read_data_from_flash_mem(buf, oob_size);
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return 0;
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}
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static int nand_read_page(void *buf, int page)
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{
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int ret;
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ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS);
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if (ret < 0)
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return ret;
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read_data_from_flash_mem(buf, page_size);
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return 0;
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}
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static int nand_block_isbad(void *buf, int block)
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{
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int ret;
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ret = nand_read_oob(buf, block * pages_per_block);
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if (ret < 0)
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return ret;
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return *((uint8_t *)buf + CONFIG_SYS_NAND_BAD_BLOCK_POS) != 0xff;
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}
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/* nand_init() - initialize data to make nand usable by SPL */
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void nand_init(void)
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{
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/* access to main area */
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writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
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/*
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* These registers are expected to be already set by the hardware
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* or earlier boot code. So we read these values out.
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*/
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page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
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oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
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pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
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/* Do as denali_hw_init() does. */
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writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
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denali_flash_reg + SPARE_AREA_SKIP_BYTES);
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writel(0x0F, denali_flash_reg + RB_PIN_ENABLED);
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writel(CHIP_EN_DONT_CARE__FLAG, denali_flash_reg + CHIP_ENABLE_DONT_CARE);
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writel(0xffff, denali_flash_reg + SPARE_AREA_MARKER);
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}
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
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{
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int block, page, column, readlen;
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int ret;
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int force_bad_block_check = 1;
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page = offs / page_size;
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column = offs % page_size;
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block = page / pages_per_block;
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page = page % pages_per_block;
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while (size) {
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if (force_bad_block_check || page == 0) {
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ret = nand_block_isbad(dst, block);
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if (ret < 0)
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return ret;
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if (ret) {
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block++;
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continue;
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}
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}
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force_bad_block_check = 0;
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ret = nand_read_page(dst, block * pages_per_block + page);
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if (ret < 0)
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return ret;
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readlen = min(page_size - column, (int)size);
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if (unlikely(column)) {
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/* Partial page read */
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memmove(dst, dst + column, readlen);
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column = 0;
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}
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size -= readlen;
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dst += readlen;
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page++;
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if (page == pages_per_block) {
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block++;
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page = 0;
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}
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}
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return 0;
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}
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void nand_deselect(void) {}
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