mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
355 lines
7.2 KiB
C
355 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009 Industrie Dial Face S.p.A.
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* Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
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*
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* (C) Copyright 2001
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* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
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*/
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/*
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* This provides a bit-banged interface to the ethernet MII management
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* channel.
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*/
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#include <common.h>
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#include <ioports.h>
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#include <ppc_asm.tmpl>
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#include <miiphy.h>
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#define BB_MII_RELOCATE(v,off) (v += (v?off:0))
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_BITBANGMII_MULTI
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/*
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* If CONFIG_BITBANGMII_MULTI is not defined we use a
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* compatibility layer with the previous miiphybb implementation
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* based on macros usage.
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*
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*/
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static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
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{
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#ifdef MII_INIT
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MII_INIT;
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#endif
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return 0;
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}
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static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
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{
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#ifdef MDIO_DECLARE
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MDIO_DECLARE;
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#endif
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MDIO_ACTIVE;
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return 0;
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}
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static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
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{
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#ifdef MDIO_DECLARE
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MDIO_DECLARE;
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#endif
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MDIO_TRISTATE;
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return 0;
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}
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static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
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{
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#ifdef MDIO_DECLARE
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MDIO_DECLARE;
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#endif
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MDIO(v);
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return 0;
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}
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static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
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{
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#ifdef MDIO_DECLARE
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MDIO_DECLARE;
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#endif
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*v = MDIO_READ;
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return 0;
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}
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static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
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{
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#ifdef MDC_DECLARE
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MDC_DECLARE;
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#endif
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MDC(v);
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return 0;
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}
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static int bb_delay_wrap(struct bb_miiphy_bus *bus)
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{
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MIIDELAY;
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return 0;
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}
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struct bb_miiphy_bus bb_miiphy_buses[] = {
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{
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.name = BB_MII_DEVNAME,
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.init = bb_mii_init_wrap,
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.mdio_active = bb_mdio_active_wrap,
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.mdio_tristate = bb_mdio_tristate_wrap,
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.set_mdio = bb_set_mdio_wrap,
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.get_mdio = bb_get_mdio_wrap,
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.set_mdc = bb_set_mdc_wrap,
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.delay = bb_delay_wrap,
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}
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};
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int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
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sizeof(bb_miiphy_buses[0]);
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#endif
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void bb_miiphy_init(void)
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{
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int i;
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for (i = 0; i < bb_miiphy_buses_num; i++) {
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#if defined(CONFIG_NEEDS_MANUAL_RELOC)
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/* Relocate the hook pointers*/
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BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
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BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
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BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off);
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BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off);
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BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off);
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BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off);
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BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off);
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#endif
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if (bb_miiphy_buses[i].init != NULL) {
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bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
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}
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}
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}
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static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
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{
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#ifdef CONFIG_BITBANGMII_MULTI
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int i;
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/* Search the correct bus */
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for (i = 0; i < bb_miiphy_buses_num; i++) {
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if (!strcmp(bb_miiphy_buses[i].name, devname)) {
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return &bb_miiphy_buses[i];
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}
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}
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return NULL;
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#else
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/* We have just one bitbanging bus */
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return &bb_miiphy_buses[0];
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#endif
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}
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/*****************************************************************************
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*
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* Utility to send the preamble, address, and register (common to read
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* and write).
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*/
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static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
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unsigned char addr, unsigned char reg)
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{
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int j;
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/*
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* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
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* The IEEE spec says this is a PHY optional requirement. The AMD
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* 79C874 requires one after power up and one after a MII communications
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* error. This means that we are doing more preambles than we need,
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* but it is safer and will be much more robust.
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*/
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bus->mdio_active(bus);
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bus->set_mdio(bus, 1);
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for (j = 0; j < 32; j++) {
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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}
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/* send the start bit (01) and the read opcode (10) or write (10) */
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, read);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, !read);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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/* send the PHY address */
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for (j = 0; j < 5; j++) {
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bus->set_mdc(bus, 0);
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if ((addr & 0x10) == 0) {
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bus->set_mdio(bus, 0);
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} else {
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bus->set_mdio(bus, 1);
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}
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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addr <<= 1;
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}
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/* send the register address */
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for (j = 0; j < 5; j++) {
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bus->set_mdc(bus, 0);
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if ((reg & 0x10) == 0) {
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bus->set_mdio(bus, 0);
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} else {
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bus->set_mdio(bus, 1);
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}
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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reg <<= 1;
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}
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}
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/*****************************************************************************
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*
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* Read a MII PHY register.
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*
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* Returns:
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* 0 on success
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*/
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int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
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{
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unsigned short rdreg; /* register working value */
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int v;
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int j; /* counter */
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struct bb_miiphy_bus *bus;
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bus = bb_miiphy_getbus(miidev->name);
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if (bus == NULL) {
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return -1;
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}
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miiphy_pre (bus, 1, addr, reg);
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/* tri-state our MDIO I/O pin so we can read */
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bus->set_mdc(bus, 0);
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bus->mdio_tristate(bus);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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/* check the turnaround bit: the PHY should be driving it to zero */
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bus->get_mdio(bus, &v);
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if (v != 0) {
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/* puts ("PHY didn't drive TA low\n"); */
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for (j = 0; j < 32; j++) {
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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}
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/* There is no PHY, return */
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return -1;
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}
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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/* read 16 bits of register data, MSB first */
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rdreg = 0;
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for (j = 0; j < 16; j++) {
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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rdreg <<= 1;
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bus->get_mdio(bus, &v);
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rdreg |= (v & 0x1);
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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}
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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#ifdef DEBUG
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printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg);
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#endif
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return rdreg;
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}
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/*****************************************************************************
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*
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* Write a MII PHY register.
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*
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* Returns:
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* 0 on success
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*/
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int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
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u16 value)
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{
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struct bb_miiphy_bus *bus;
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int j; /* counter */
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bus = bb_miiphy_getbus(miidev->name);
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if (bus == NULL) {
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/* Bus not found! */
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return -1;
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}
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miiphy_pre (bus, 0, addr, reg);
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/* send the turnaround (10) */
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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/* write 16 bits of register data, MSB first */
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for (j = 0; j < 16; j++) {
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bus->set_mdc(bus, 0);
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if ((value & 0x00008000) == 0) {
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bus->set_mdio(bus, 0);
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} else {
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bus->set_mdio(bus, 1);
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}
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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value <<= 1;
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}
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/*
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* Tri-state the MDIO line.
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*/
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bus->mdio_tristate(bus);
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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return 0;
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}
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