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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 11:46:17 +09:00
6bf238a461
Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
59 lines
1.3 KiB
Plaintext
59 lines
1.3 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_SYS_TEXT_BASE=0x1000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
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CONFIG_IDENT_STRING="socfpga_stratix10"
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CONFIG_SPL_FS_FAT=y
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CONFIG_BOOTDELAY=5
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CONFIG_SPL_TEXT_BASE=0xFFE00000
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_EMBED=y
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_ALTERA_SDRAM=y
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CONFIG_DM_GPIO=y
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CONFIG_DWAPB_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_DW=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_DW=y
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CONFIG_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0x2003
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_MII=y
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CONFIG_DM_RESET=y
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CONFIG_SPI=y
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CONFIG_CADENCE_QSPI=y
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CONFIG_DESIGNWARE_SPI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_STORAGE=y
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