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https://github.com/brain-hackers/u-boot-brain
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5d6050fdb8
This patch adds the new Barco platinum platform. It currently includes those two boards: platinum-titanium ----------------- This is the same board as the titanium that is already supported in mainline U-Boot. But its now moved to this new platform to support multiple "flavors" of imx6 boards in one directory. Its also moved to support SPL booting. And with this we use the run-time DDR configuration of this SPL support. The board is equipped with the Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR related registers tuples from the imximage.cfg file. As all this is done in the SPL at run-time. platinum-picon -------------- This board is new and based on the MX6DL with 1GiB DDR using the Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND chips (each 512MiB). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Pieter Ronsijn <pieter.ronsijn@barco.com>
186 lines
4.8 KiB
C
186 lines
4.8 KiB
C
/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* Based on: gw_ventana_spl.c which is:
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* Copyright (C) 2014 Gateworks Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <spl.h>
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#include "platinum.h"
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DECLARE_GLOBAL_DATA_PTR;
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#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
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/* Configure MX6Q/DUAL mmdc DDR io registers */
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struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
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.dram_sdclk_0 = 0x00020030,
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.dram_sdclk_1 = 0x00020030,
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.dram_cas = 0x00020030,
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.dram_ras = 0x00020030,
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.dram_reset = 0x00020030,
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/* SDCKE[0:1]: 100k pull-up */
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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/* SDBA2: pull-up disabled */
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.dram_sdba2 = 0x00000000,
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/* SDODT[0:1]: 100k pull-up, 40 ohm */
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.dram_sdodt0 = 0x00003030,
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.dram_sdodt1 = 0x00003030,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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/* DQM[0:7]: Differential input, 40 ohm */
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.dram_dqm0 = 0x00020030,
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.dram_dqm1 = 0x00020030,
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.dram_dqm2 = 0x00020030,
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.dram_dqm3 = 0x00020030,
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.dram_dqm4 = 0x00020030,
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.dram_dqm5 = 0x00020030,
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.dram_dqm6 = 0x00020030,
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.dram_dqm7 = 0x00020030,
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};
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/* Configure MX6Q/DUAL mmdc GRP io registers */
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struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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/* DDR3 */
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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/* disable DDR pullups */
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.grp_ddrpke = 0x00000000,
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/* ADDR[00:16], SDBA[0:1]: 40 ohm */
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.grp_addds = 0x00000030,
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
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.grp_ctlds = 0x00000030,
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/* DATA[00:63]: Differential input, 40 ohm */
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_b4ds = 0x00000030,
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.grp_b5ds = 0x00000030,
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.grp_b6ds = 0x00000030,
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.grp_b7ds = 0x00000030,
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};
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/* MT41J128M16JT-125 */
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static struct mx6_ddr3_cfg mt41j128m16jt_125 = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
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/* Write leveling calibration determine */
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.p0_mpwldectrl0 = 0x001f001f,
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.p0_mpwldectrl1 = 0x001f001f,
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.p1_mpwldectrl0 = 0x00440044,
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.p1_mpwldectrl1 = 0x00440044,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x434b0350,
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.p0_mpdgctrl1 = 0x034c0359,
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.p1_mpdgctrl0 = 0x434b0350,
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.p1_mpdgctrl1 = 0x03650348,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x4436383b,
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.p1_mprddlctl = 0x39393341,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x35373933,
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.p1_mpwrdlctl = 0x48254a36,
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};
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static void spl_dram_init(int width)
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{
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struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125;
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = width / 32,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* single chip select */
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.ncs = 1,
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.cs1_mirror = 1,
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
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#ifdef RTT_NOM_120OHM
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.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
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#else
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.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
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#endif
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.walat = 0, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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};
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mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
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}
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/*
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* Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
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* - we have a stack and a place to store GD, both in SRAM
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* - no variable global data is available
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*/
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void board_init_f(ulong dummy)
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{
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/* Setup AIPS and disable watchdog */
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arch_cpu_init();
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ccgr_init();
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gpr_init();
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/* UART iomux */
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board_early_init_f();
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/* Setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* Init DDR with 32bit width */
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spl_dram_init(32);
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/* Clear the BSS */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/*
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* Setup enet related MUXing early to give the PHY
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* some time to wake-up from reset
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*/
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platinum_setup_enet();
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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