mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
![Jerome Brunet](/assets/img/avatar_default.png)
Sync the device tree and dt-bindings from Linux v5.6-rc2 11a48a5a18c6 ("Linux 5.6-rc2") The only exception to this is the mmc pinctrl pin bias of gxl SoC family. This is a fix which found its way to u-boot but not Linux yet. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2019 BayLibre, SAS
|
|
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
|
* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "meson-g12b-a311d.dtsi"
|
|
#include "meson-khadas-vim3.dtsi"
|
|
#include "meson-g12b-khadas-vim3.dtsi"
|
|
|
|
/ {
|
|
compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b";
|
|
};
|
|
|
|
/*
|
|
* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
|
|
* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
|
|
* an USB3.0 Type A connector and a M.2 Key M slot.
|
|
* The PHY driving these differential lines is shared between
|
|
* the USB3.0 controller and the PCIe Controller, thus only
|
|
* a single controller can use it.
|
|
* If the MCU is configured to mux the PCIe/USB3.0 differential lines
|
|
* to the M.2 Key M slot, uncomment the following block to disable
|
|
* USB3.0 from the USB Complex and enable the PCIe controller.
|
|
* The End User is not expected to uncomment the following except for
|
|
* testing purposes, but instead rely on the firmware/bootloader to
|
|
* update these nodes accordingly if PCIe mode is selected by the MCU.
|
|
*/
|
|
/*
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb {
|
|
phys = <&usb2_phy0>, <&usb2_phy1>;
|
|
phy-names = "usb2-phy0", "usb2-phy1";
|
|
};
|
|
*/
|