mirror of
https://github.com/brain-hackers/u-boot-brain
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587c3f8ebe
The problem is that timeout bits in WCR register were leaved unchanged. So previously set timeout value was applied and therefore 'reset' command takes any value up to two minutes, depending on previous watchdog settings, instead of minimal 0.5 seconds. Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
/*
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* watchdog.c - driver for i.mx on-chip watchdog
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <watchdog.h>
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#include <asm/arch/imx-regs.h>
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#include <fsl_wdog.h>
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#ifdef CONFIG_IMX_WATCHDOG
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void hw_watchdog_reset(void)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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writew(0x5555, &wdog->wsr);
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writew(0xaaaa, &wdog->wsr);
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}
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void hw_watchdog_init(void)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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u16 timeout;
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/*
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* The timer watchdog can be set between
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* 0.5 and 128 Seconds. If not defined
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* in configuration file, sets 128 Seconds
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*/
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#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
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#endif
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timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
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writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
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SET_WCR_WT(timeout), &wdog->wcr);
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hw_watchdog_reset();
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}
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#endif
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void reset_cpu(ulong addr)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
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writew(0x5555, &wdog->wsr);
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writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
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while (1) {
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/*
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* spin for .5 seconds before reset
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*/
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}
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}
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