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u-boot-brain/board/freescale/ls2085a
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York Sun 8bfa301b0a ARMv8/ls2085a: Enable secondary cores 
Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.

Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-25 08:36:19 -07:00
..
ddr.c ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory block 2014-09-25 08:36:18 -07:00
ddr.h ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory block 2014-09-25 08:36:18 -07:00
Kconfig kconfig: armv8: move CONFIG_ARM64 to Kconfig 2014-09-16 12:24:00 -04:00
ls2085a.c ARMv8/ls2085a: Enable secondary cores 2014-09-25 08:36:19 -07:00
MAINTAINERS Add board MAINTAINERS files 2014-07-30 08:48:06 -04:00
Makefile ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support 2014-07-04 19:48:41 +02:00
README ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support 2014-07-04 19:48:41 +02:00

README 

Freescale ls2085a_emu

This is a emulator target with limited peripherals.

Memory map from core's view

0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
0x80_8000_0000 .. 0xFF_FFFF_FFFF	DDR region #2

Other addresses are either reserved, or not used directly by u-boot.
This list should be updated when more addresses are used.