mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
126 lines
3.6 KiB
C
126 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Bluewater Systems Snapper 9260 and 9G20 modules
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*
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* (C) Copyright 2011 Bluewater Systems
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* Author: Andre Renaud <andre@bluewatersys.com>
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* Author: Ryan Mallon <ryan@bluewatersys.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* SoC type is defined in boards.cfg */
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#include <asm/hardware.h>
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#include <linux/sizes.h>
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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/* CPU */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
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#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
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GENERATED_GBL_DATA_SIZE)
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/* Mem test settings */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
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/* NAND Flash */
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
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/* Ethernet */
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_RESET_PHY_R
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#define CONFIG_AT91_WANTS_COMMON_PHY
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#define CONFIG_TFTP_PORT
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#define CONFIG_TFTP_TSIZE
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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/* GPIOs and IO expander */
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#define CONFIG_ATMEL_LEGACY
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#define CONFIG_AT91_GPIO
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#define CONFIG_AT91_GPIO_PULLUP 1
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#define CONFIG_PCA953X
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#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
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#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
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/* UARTs/Serial console */
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#define CONFIG_ATMEL_USART
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#ifndef CONFIG_DM_SERIAL
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#endif
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/* I2C - Bit-bashed */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SOFT_SPEED 100000
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
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#define CONFIG_SOFT_I2C_READ_REPEATED_START
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#define I2C_INIT do { \
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at91_set_gpio_output(AT91_PIN_PA23, 1); \
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at91_set_gpio_output(AT91_PIN_PA24, 1); \
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at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
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at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
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} while (0)
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#define I2C_SOFT_DECLARATIONS
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#define I2C_ACTIVE
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#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
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#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
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#define I2C_SDA(bit) do { \
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if (bit) { \
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at91_set_gpio_input(AT91_PIN_PA23, 1); \
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} else { \
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at91_set_gpio_output(AT91_PIN_PA23, 1); \
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at91_set_gpio_value(AT91_PIN_PA23, bit); \
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} \
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} while (0)
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#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
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#define I2C_DELAY udelay(2)
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/* Boot options */
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#define CONFIG_SYS_LOAD_ADDR 0x23000000
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* Environment settings */
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#define CONFIG_ENV_OFFSET (512 << 10)
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#define CONFIG_ENV_SIZE (256 << 10)
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#define CONFIG_ENV_OVERWRITE
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/* Console settings */
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/* U-Boot memory settings */
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#define CONFIG_SYS_MALLOC_LEN (1 << 20)
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#endif /* __CONFIG_H */
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