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https://github.com/brain-hackers/u-boot-brain
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a6e50a88d8
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included. The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented. The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef. This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
192 lines
5.1 KiB
C
192 lines
5.1 KiB
C
/*
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* sun4i, sun5i and sun7i specific clock code
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*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#ifdef CONFIG_SPL_BUILD
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void clock_init_safe(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* Set safe defaults until PMU is configured */
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writel(AXI_DIV_1 << AXI_DIV_SHIFT |
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AHB_DIV_2 << AHB_DIV_SHIFT |
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APB0_DIV_1 << APB0_DIV_SHIFT |
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CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_ahb_apb0_cfg);
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writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
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sdelay(200);
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writel(AXI_DIV_1 << AXI_DIV_SHIFT |
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AHB_DIV_2 << AHB_DIV_SHIFT |
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APB0_DIV_1 << APB0_DIV_SHIFT |
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CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_ahb_apb0_cfg);
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#ifdef CONFIG_SUN7I
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setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
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#endif
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writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
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#ifdef CONFIG_SUNXI_AHCI
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setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
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setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
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#endif
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}
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#endif
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void clock_init_uart(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* uart clock source is apb1 */
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writel(APB1_CLK_SRC_OSC24M|
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APB1_CLK_RATE_N_1|
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APB1_CLK_RATE_M(1),
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&ccm->apb1_clk_div_cfg);
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/* open the clock for uart */
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setbits_le32(&ccm->apb1_gate,
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CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
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}
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int clock_twi_onoff(int port, int state)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (port > 2)
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return -1;
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/* set the apb clock gate for twi */
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if (state)
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setbits_le32(&ccm->apb1_gate,
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CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
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else
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clrbits_le32(&ccm->apb1_gate,
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CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
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0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \
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8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
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0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
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16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
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(P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
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2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
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(N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
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(K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
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0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
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0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
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(M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
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static struct {
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u32 pll1_cfg;
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unsigned int freq;
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} pll1_para[] = {
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/* This array must be ordered by frequency. */
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{ PLL1_CFG(16, 0, 0, 0), 384000000 },
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{ PLL1_CFG(16, 1, 0, 0), 768000000 },
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{ PLL1_CFG(20, 1, 0, 0), 960000000 },
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{ PLL1_CFG(21, 1, 0, 0), 1008000000},
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{ PLL1_CFG(22, 1, 0, 0), 1056000000},
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{ PLL1_CFG(23, 1, 0, 0), 1104000000},
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{ PLL1_CFG(24, 1, 0, 0), 1152000000},
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{ PLL1_CFG(25, 1, 0, 0), 1200000000},
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{ PLL1_CFG(26, 1, 0, 0), 1248000000},
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{ PLL1_CFG(27, 1, 0, 0), 1296000000},
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{ PLL1_CFG(28, 1, 0, 0), 1344000000},
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{ PLL1_CFG(29, 1, 0, 0), 1392000000},
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{ PLL1_CFG(30, 1, 0, 0), 1440000000},
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{ PLL1_CFG(31, 1, 0, 0), 1488000000},
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/* Final catchall entry */
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{ PLL1_CFG(31, 1, 0, 0), ~0},
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};
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void clock_set_pll1(unsigned int hz)
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{
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int i = 0;
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int axi, ahb, apb0;
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* Find target frequency */
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while (pll1_para[i].freq < hz)
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i++;
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hz = pll1_para[i].freq;
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/* Calculate system clock divisors */
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axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */
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ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */
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apb0 = 2; /* Max 150MHz */
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printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
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/* Map divisors to register values */
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axi = axi - 1;
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if (ahb > 4)
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ahb = 3;
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else if (ahb > 2)
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ahb = 2;
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else if (ahb > 1)
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ahb = 1;
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else
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ahb = 0;
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apb0 = apb0 - 1;
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/* Switch to 24MHz clock while changing PLL1 */
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writel(AXI_DIV_1 << AXI_DIV_SHIFT |
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AHB_DIV_2 << AHB_DIV_SHIFT |
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APB0_DIV_1 << APB0_DIV_SHIFT |
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CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_ahb_apb0_cfg);
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sdelay(20);
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/* Configure sys clock divisors */
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writel(axi << AXI_DIV_SHIFT |
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ahb << AHB_DIV_SHIFT |
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apb0 << APB0_DIV_SHIFT |
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CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_ahb_apb0_cfg);
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/* Configure PLL1 at the desired frequency */
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writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
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sdelay(200);
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/* Switch CPU to PLL1 */
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writel(axi << AXI_DIV_SHIFT |
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ahb << AHB_DIV_SHIFT |
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apb0 << APB0_DIV_SHIFT |
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CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_ahb_apb0_cfg);
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sdelay(20);
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}
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#endif
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unsigned int clock_get_pll6(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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uint32_t rval = readl(&ccm->pll6_cfg);
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int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
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int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
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return 24000000 * n * k / 2;
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}
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