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61bd2f75f5
u-boot-brain/arch/arm/include/asm/arch-fsl-layerscape
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York Sun 61bd2f75f5 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
..
clock.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
config.h drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 2015-11-30 09:11:11 -08:00
cpu.h armv8: ls2085a: Add support of LS2085A SoC 2015-11-30 09:10:47 -08:00
fdt.h armv8/ls1043aqds: add LS1043AQDS board support 2015-11-30 09:11:10 -08:00
fsl_serdes.h armv8: ls2085a: Add support of LS2085A SoC 2015-11-30 09:10:47 -08:00
immap_lsch2.h armv8/ls1043ardb: add USB support 2015-11-30 09:11:11 -08:00
immap_lsch3.h pci/layerscape: add support for LS1043A PCIe LUT register access 2015-11-30 09:11:10 -08:00
imx-regs.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
ls2080a_stream_id.h armv8: LS2080A: Rename LS2085A to reflect LS2080A 2015-11-30 08:53:04 -08:00
mmu.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
mp.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
ns_access.h armv8/fsl_lsch2: Add fsl_lsch2 SoC 2015-10-29 10:34:00 -07:00
soc.h pci/layerscape: add support for LS1043A PCIe LUT register access 2015-11-30 09:11:10 -08:00
speed.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00