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![]() Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com> |
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.. | ||
clock.h | ||
config.h | ||
cpu.h | ||
fdt.h | ||
fsl_serdes.h | ||
immap_lsch2.h | ||
immap_lsch3.h | ||
imx-regs.h | ||
ls2080a_stream_id.h | ||
mmu.h | ||
mp.h | ||
ns_access.h | ||
soc.h | ||
speed.h |