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![wdenk](/assets/img/avatar_default.png)
- creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200 - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
211 lines
4.6 KiB
C
211 lines
4.6 KiB
C
/*
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* (C) Copyright 2002
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* Lineo, Inc. <www.lineo.com>
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* Bernhard Kuhn <bkuhn@lineo.com>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/*#include <asm/io.h>*/
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#include <asm/arch/hardware.h>
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/*#include <asm/proc/ptrace.h>*/
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/* the number of clocks per CFG_HZ */
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#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
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/* macro to read the 16 bit timer */
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#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
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AT91PS_TC tmr;
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static ulong timestamp;
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static ulong lastinc;
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int interrupt_init (void)
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{
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tmr = AT91C_BASE_TC0;
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/* enables TC1.0 clock */
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*AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */
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*AT91C_TCB0_BCR = 0;
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*AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
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tmr->TC_CCR = AT91C_TC_CLKDIS;
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#define AT91C_TC_CMR_CPCTRG (1 << 14)
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/* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
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tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
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tmr->TC_IDR = ~0ul;
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tmr->TC_RC = TIMER_LOAD_VAL;
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lastinc = 0;
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tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
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timestamp = 0;
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return (0);
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}
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/*
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* timer without interrupts
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*/
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void reset_timer (void)
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{
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reset_timer_masked ();
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}
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ulong get_timer (ulong base)
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{
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return get_timer_masked () - base;
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}
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void set_timer (ulong t)
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{
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timestamp = t;
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}
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void udelay (unsigned long usec)
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{
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udelay_masked(usec);
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}
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void reset_timer_masked (void)
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{
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/* reset time */
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lastinc = READ_TIMER;
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timestamp = 0;
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}
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ulong get_timer_raw (void)
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{
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ulong now = READ_TIMER;
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if (now >= lastinc) {
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/* normal mode */
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timestamp += now - lastinc;
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} else {
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/* we have an overflow ... */
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timestamp += now + TIMER_LOAD_VAL - lastinc;
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}
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lastinc = now;
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return timestamp;
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}
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ulong get_timer_masked (void)
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{
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return get_timer_raw()/TIMER_LOAD_VAL;
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}
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void udelay_masked (unsigned long usec)
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{
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ulong tmo;
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ulong endtime;
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signed long diff;
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tmo = CFG_HZ_CLOCK / 1000;
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tmo *= usec;
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tmo /= 1000;
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endtime = get_timer_raw () + tmo;
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do {
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ulong now = get_timer_raw ();
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diff = endtime - now;
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} while (diff >= 0);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk (void)
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{
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ulong tbclk;
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tbclk = CFG_HZ;
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return tbclk;
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}
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/*
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* Reset the cpu by setting up the watchdog timer and let him time out
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* or toggle a GPIO pin on the AT91RM9200DK board
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*/
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void reset_cpu (ulong ignored)
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{
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#ifdef CONFIG_DBGU
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AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
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#endif
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#ifdef CONFIG_USART0
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AT91PS_USART us = AT91C_BASE_US0;
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#endif
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#ifdef CONFIG_USART1
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AT91PS_USART us = AT91C_BASE_US1;
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#endif
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#ifdef CONFIG_AT91RM9200DK
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AT91PS_PIO pio = AT91C_BASE_PIOA;
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#endif
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/*shutdown the console to avoid strange chars during reset */
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us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
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#ifdef CONFIG_AT91RM9200DK
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/* Clear PA19 to trigger the hard reset */
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pio->PIO_CODR = 0x00080000;
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pio->PIO_OER = 0x00080000;
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pio->PIO_PER = 0x00080000;
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#endif
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/* this is the way Linux does it */
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/* FIXME:
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* These defines should be moved into
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* include/asm-arm/arch-at91rm9200/AT91RM9200.h
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* as soon as the whitespace fix gets applied.
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*/
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#define AT91C_ST_RSTEN (0x1 << 16)
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#define AT91C_ST_EXTEN (0x1 << 17)
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#define AT91C_ST_WDRST (0x1 << 0)
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#define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */
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#define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */
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ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
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ST_CR = AT91C_ST_WDRST;
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while (1);
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/* Never reached */
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}
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