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https://github.com/brain-hackers/u-boot-brain
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61293f519e
In current code there is no cache flush after initializing the scratchpad buffer array with the scratchpad buffer pointers. This leads to a failure of the "slot enable" command on the rpi4 board (Broadcom STB PCIe controller + VL805 USB hub) - the very first TRB transfer on the command ring fails and there is a timeout while waiting for the command completion event. After adding the missing cache flush everything seems to be working as expected. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
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| .. | ||
| cdns3 | ||
| common | ||
| dwc3 | ||
| emul | ||
| eth | ||
| gadget | ||
| host | ||
| musb | ||
| musb-new | ||
| phy | ||
| ulpi | ||
| Kconfig | ||