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https://github.com/brain-hackers/u-boot-brain
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37fa41256b
The config block support currently uses the ft_board_setup function to patch the device tree with config block information. However, this does not allow to patch the device tree with board specific information. Rename the common setup function to ft_common_board_setup and use the call it from the board files directly. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
155 lines
3.5 KiB
C
155 lines
3.5 KiB
C
/*
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* Copyright (C) 2012 Lucas Stach
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/board.h>
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#include <asm/arch-tegra/tegra.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include <nand.h>
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#include "../common/tdx-common.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define PMU_I2C_ADDRESS 0x34
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#define MAX_I2C_RETRY 3
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#define PMU_SUPPLYENE 0x14
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#define PMU_SUPPLYENE_SYSINEN (1<<5)
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#define PMU_SUPPLYENE_EXITSLREQ (1<<1)
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int arch_misc_init(void)
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{
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/* Disable PMIC sleep mode on low supply voltage */
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struct udevice *dev;
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u8 addr, data[1];
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int err;
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err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
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if (err) {
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debug("%s: Cannot find PMIC I2C chip\n", __func__);
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return err;
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}
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addr = PMU_SUPPLYENE;
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err = dm_i2c_read(dev, addr, data, 1);
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if (err) {
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debug("failed to get PMU_SUPPLYENE\n");
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return err;
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}
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data[0] &= ~PMU_SUPPLYENE_SYSINEN;
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data[0] |= PMU_SUPPLYENE_EXITSLREQ;
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err = dm_i2c_write(dev, addr, data, 1);
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if (err) {
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debug("failed to set PMU_SUPPLYENE\n");
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return err;
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}
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/* make sure SODIMM pin 87 nRESET_OUT is released properly */
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pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);
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if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
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NVBOOTTYPE_RECOVERY)
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printf("USB recovery mode\n");
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return 0;
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}
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int checkboard(void)
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{
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printf("Model: Toradex Colibri T20 %dMB V%s\n",
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(gd->ram_size == 0x10000000) ? 256 : 512,
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(nand_info[0]->erasesize >> 10 == 512) ?
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((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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return ft_common_board_setup(blob, bd);
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}
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#endif
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#ifdef CONFIG_TEGRA_MMC
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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void pin_mux_mmc(void)
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{
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funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
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pinmux_tristate_disable(PMUX_PINGRP_GMB);
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}
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#endif
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#ifdef CONFIG_TEGRA_NAND
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void pin_mux_nand(void)
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{
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funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
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/*
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* configure pingroup ATC to something unrelated to
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* avoid ATC overriding KBC
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*/
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pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
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}
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#endif
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#ifdef CONFIG_USB_EHCI_TEGRA
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void pin_mux_usb(void)
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{
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/* module internal USB bus to connect ethernet chipset */
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funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
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/* ULPI reference clock output */
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pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
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pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
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/* PHY reset GPIO */
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pinmux_tristate_disable(PMUX_PINGRP_UAC);
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/* VBus GPIO */
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pinmux_tristate_disable(PMUX_PINGRP_DTE);
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/* Reset ASIX using LAN_RESET */
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gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
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gpio_direction_output(TEGRA_GPIO(V, 4), 0);
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pinmux_tristate_disable(PMUX_PINGRP_GPV);
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udelay(5);
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gpio_set_value(TEGRA_GPIO(V, 4), 1);
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/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
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pinmux_tristate_disable(PMUX_PINGRP_SPIG);
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}
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#endif
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#ifdef CONFIG_VIDEO_TEGRA20
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/*
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* Routine: pin_mux_display
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* Description: setup the pin muxes/tristate values for the LCD interface)
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*/
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void pin_mux_display(void)
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{
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/*
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* Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
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* device-tree
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*/
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pinmux_tristate_disable(PMUX_PINGRP_DTA);
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pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
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pinmux_tristate_disable(PMUX_PINGRP_SDC);
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}
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#endif
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