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https://github.com/brain-hackers/u-boot-brain
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![Ryder Lee](/assets/img/avatar_default.png)
This patch adds clock modules for MediaTek SoCs: - Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future. - Specific SoC part: the group of structures used to hold the hardware configuration for each SoC. We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
37 lines
1.2 KiB
Makefile
37 lines
1.2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2015 Google, Inc
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
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obj-y += imx/
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obj-y += tegra/
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obj-$(CONFIG_ARCH_ASPEED) += aspeed/
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obj-$(CONFIG_ARCH_MESON) += clk_meson.o
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obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_ARCH_SOCFPGA) += altera/
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obj-$(CONFIG_CLK_AT91) += at91/
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obj-$(CONFIG_CLK_MVEBU) += mvebu/
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obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
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obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
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obj-$(CONFIG_CLK_EXYNOS) += exynos/
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
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obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
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obj-$(CONFIG_CLK_OWL) += owl/
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obj-$(CONFIG_CLK_RENESAS) += renesas/
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obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
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obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
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obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
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obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
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obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
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obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
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obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
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obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
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obj-$(CONFIG_STM32H7) += clk_stm32h7.o
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obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
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