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60a996bacb
STM32F4 serial IP is similar to F7 and H7, but registers are not located at the same offset and some feature are only supported by F7 and H7 version. Registers offset must be added for each version and also some flags indicated the supported feature. Update registers name to match with datasheet (sr to isr, rx_dr to rdr and tx_dr to tdr) and remove unused regs (cr2, gtpr, rtor, and rqr). Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
56 lines
1.3 KiB
C
56 lines
1.3 KiB
C
/*
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* (C) Copyright 2016
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* Vikas Manocha, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SERIAL_STM32_X7_
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#define _SERIAL_STM32_X7_
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#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
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#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
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#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
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#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
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/*
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* STM32F4 has one Data Register (DR) for received or transmitted
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* data, so map Receive Data Register (RDR) and Transmit Data
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* Register (TDR) at the same offset
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*/
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#define RDR_OFFSET(x) (x ? 0x04 : 0x24)
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#define TDR_OFFSET(x) (x ? 0x04 : 0x28)
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struct stm32_uart_info {
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u8 uart_enable_bit; /* UART_CR1_UE */
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bool stm32f4; /* true for STM32F4, false otherwise */
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bool has_overrun_disable;
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};
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struct stm32_uart_info stm32x7_info = {
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.uart_enable_bit = 0,
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.stm32f4 = false,
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.has_overrun_disable = true,
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};
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/* Information about a serial port */
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struct stm32x7_serial_platdata {
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fdt_addr_t base; /* address of registers in physical memory */
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struct stm32_uart_info *uart_info;
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unsigned long int clock_rate;
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};
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#define USART_CR1_OVER8 BIT(15)
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#define USART_CR1_TE BIT(3)
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#define USART_CR1_RE BIT(2)
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#define USART_CR3_OVRDIS BIT(12)
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#define USART_SR_FLAG_RXNE BIT(5)
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#define USART_SR_FLAG_TXE BIT(7)
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#define USART_BRR_F_MASK GENMASK(7, 0)
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#define USART_BRR_M_SHIFT 4
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#define USART_BRR_M_MASK GENMASK(15, 4)
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#endif
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