mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 11:29:43 +09:00
60570df19c
Add the stm32F4 board's serial ports support. User can use it easily. The user only need to edit the number of the usart. The patch also fix the serial print out. Last, this version of patch fix the first patch checkpatch.pl error. Thanks to Kamil Lulko. Signed-off-by: kunhuahuang <huangkunhua@gmail.com>
288 lines
7.8 KiB
C
288 lines
7.8 KiB
C
/*
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* (C) Copyright 2011, 2012, 2013
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* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
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* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
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* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
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* Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
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*
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* (C) Copyright 2015
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* Kamil Lulko, <rev13@wp.pl>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/armv7m.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/fmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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const struct stm32_gpio_ctl gpio_ctl_gpout = {
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.mode = STM32_GPIO_MODE_OUT,
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.otype = STM32_GPIO_OTYPE_PP,
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.speed = STM32_GPIO_SPEED_50M,
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.pupd = STM32_GPIO_PUPD_NO,
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.af = STM32_GPIO_AF0
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};
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const struct stm32_gpio_ctl gpio_ctl_usart = {
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.mode = STM32_GPIO_MODE_AF,
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.otype = STM32_GPIO_OTYPE_PP,
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.speed = STM32_GPIO_SPEED_50M,
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.pupd = STM32_GPIO_PUPD_UP,
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.af = STM32_GPIO_USART
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};
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static const struct stm32_gpio_dsc usart_gpio[] = {
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{STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */
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{STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */
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};
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int uart_setup_gpio(void)
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{
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int i;
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int rv = 0;
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for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
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rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
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if (rv)
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goto out;
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}
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out:
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return rv;
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}
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const struct stm32_gpio_ctl gpio_ctl_fmc = {
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.mode = STM32_GPIO_MODE_AF,
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.otype = STM32_GPIO_OTYPE_PP,
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.speed = STM32_GPIO_SPEED_100M,
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.pupd = STM32_GPIO_PUPD_NO,
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.af = STM32_GPIO_AF12
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};
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static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
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/* Chip is LQFP144, see DM00077036.pdf for details */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
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{STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
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{STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
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{STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */
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{STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
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{STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */
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{STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */
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{STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
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};
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static int fmc_setup_gpio(void)
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{
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int rv = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
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rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
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&gpio_ctl_fmc);
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if (rv)
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goto out;
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}
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out:
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return rv;
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}
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/*
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* STM32 RCC FMC specific definitions
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*/
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#define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */
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static inline u32 _ns2clk(u32 ns, u32 freq)
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{
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u32 tmp = freq/1000000;
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return (tmp * ns) / 1000;
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}
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#define NS2CLK(ns) (_ns2clk(ns, freq))
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/*
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* Following are timings for IS42S16400J, from corresponding datasheet
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*/
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#define SDRAM_CAS 3 /* 3 cycles */
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#define SDRAM_NB 1 /* Number of banks */
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#define SDRAM_MWID 1 /* 16 bit memory */
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#define SDRAM_NR 0x1 /* 12-bit row */
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#define SDRAM_NC 0x0 /* 8-bit col */
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#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
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#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
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#define SDRAM_TRRD (NS2CLK(14) - 1)
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#define SDRAM_TRCD (NS2CLK(15) - 1)
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#define SDRAM_TRP (NS2CLK(15) - 1)
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#define SDRAM_TRAS (NS2CLK(42) - 1)
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#define SDRAM_TRC (NS2CLK(63) - 1)
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#define SDRAM_TRFC (NS2CLK(63) - 1)
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#define SDRAM_TCDL (1 - 1)
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#define SDRAM_TRDL (2 - 1)
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#define SDRAM_TBDL (1 - 1)
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#define SDRAM_TREF 1386
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#define SDRAM_TCCD (1 - 1)
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#define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */
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#define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */
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/* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */
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#define SDRAM_TWR max(\
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(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \
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(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\
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)
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#define SDRAM_MODE_BL_SHIFT 0
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#define SDRAM_MODE_CAS_SHIFT 4
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#define SDRAM_MODE_BL 0
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#define SDRAM_MODE_CAS SDRAM_CAS
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int dram_init(void)
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{
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u32 freq;
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int rv;
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rv = fmc_setup_gpio();
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if (rv)
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return rv;
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setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
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/*
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* Get frequency for NS2CLK calculation.
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*/
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freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
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writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
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| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
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| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
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&STM32_SDRAM_FMC->sdcr1);
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writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
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| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
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| SDRAM_NB << FMC_SDCR_NB_SHIFT
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| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
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| SDRAM_NR << FMC_SDCR_NR_SHIFT
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| SDRAM_NC << FMC_SDCR_NC_SHIFT
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| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
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| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
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&STM32_SDRAM_FMC->sdcr2);
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writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT
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| SDRAM_TRC << FMC_SDTR_TRC_SHIFT,
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&STM32_SDRAM_FMC->sdtr1);
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writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
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| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
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| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
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| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
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| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
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| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
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| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
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&STM32_SDRAM_FMC->sdtr2);
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writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK,
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&STM32_SDRAM_FMC->sdcmr);
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udelay(200); /* 200 us delay, page 10, "Power-Up" */
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FMC_BUSY_WAIT();
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writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE,
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&STM32_SDRAM_FMC->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT();
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writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH
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| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT();
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writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
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| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
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<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
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&STM32_SDRAM_FMC->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT();
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writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL,
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&STM32_SDRAM_FMC->sdcmr);
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FMC_BUSY_WAIT();
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/* Refresh timer */
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writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
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/*
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* Fill in global info with description of SRAM configuration
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
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gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
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gd->ram_size = CONFIG_SYS_RAM_SIZE;
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return rv;
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}
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u32 get_board_rev(void)
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{
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return 0;
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}
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int board_early_init_f(void)
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{
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int res;
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res = uart_setup_gpio();
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if (res)
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return res;
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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