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https://github.com/brain-hackers/u-boot-brain
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c99512d6bd
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
419 lines
12 KiB
C
419 lines
12 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
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*
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* TOP5200 differences from IceCube:
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* 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
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* bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
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* 1 SDRAM/DDRAM Bank up to 256 MB
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* local VPD I2C Bus is software driven and uses
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* GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
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* FLASH is re-located at 0xff000000
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* Internal regs are at 0xf0000000
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* Reset jumps to 0x00000100
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
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#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
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#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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# define CONFIG_PCI 1
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# define CONFIG_PCI_PNP 1
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# define CONFIG_PCI_SCAN_SHOW 1
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# define CONFIG_PCI_MEM_BUS 0x40000000
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# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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# define CONFIG_PCI_MEM_SIZE 0x10000000
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# define CONFIG_PCI_IO_BUS 0x50000000
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# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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# define CONFIG_PCI_IO_SIZE 0x01000000
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# define ADD_PCI_CMD CFG_CMD_PCI
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#else /* no Evaluation board */
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# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
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#endif
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/* USB */
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#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
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# define CONFIG_USB_OHCI
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# define CONFIG_USB_CLOCK 0x0001bbbb
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# if defined (CONFIG_EVAL5200)
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# define CONFIG_USB_CONFIG 0x00005100
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# else
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# define CONFIG_USB_CONFIG 0x00001000
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# endif
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# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
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# define CONFIG_DOS_PARTITION
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# define CONFIG_USB_STORAGE
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#else
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# define ADD_USB_CMD 0
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#endif
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/* IDE */
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#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
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# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT
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# define CONFIG_DOS_PARTITION
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#else
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# define ADD_IDE_CMD 0
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#endif
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/*
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* Supported commands
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*/
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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ADD_PCI_CMD | \
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ADD_USB_CMD | \
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ADD_IDE_CMD | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_I2C | \
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CFG_CMD_EEPROM | \
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CFG_CMD_REGINFO | \
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CFG_CMD_IMMAP | \
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CFG_CMD_ELF | \
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CFG_CMD_MII | \
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CFG_CMD_BEDBUG \
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)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* MUST be low boot - HIGHBOOT is not supported anymore
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*/
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#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
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# define CFG_LOWBOOT 1
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# define CFG_LOWBOOT16 1
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#else
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# error "TEXT_BASE must be 0xff000000"
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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"bootfile=/tftpboot/MPC5200/uImage\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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/*
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* IPB Bus clocking configuration.
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*/
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#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/*
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* I2C configuration
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*/
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/*
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* EEPROM configuration
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*/
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_EEPROM_SIZE 0x2000
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_MISC_INIT_R
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
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#if defined (CONFIG_SOFT_I2C)
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# define SDA0 0x40
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# define SCL0 0x80
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# define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00))
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# define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08))
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# define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c))
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# define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20))
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# define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04))
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# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
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# define I2C_READ ((DVI0&SDA0)?1:0)
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# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
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# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
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# define I2C_DELAY {udelay(5);}
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# define I2C_ACTIVE {DDR0|=SDA0;}
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# define I2C_TRISTATE {DDR0&=~SDA0;}
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# define CFG_I2C_SPEED 100000
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# define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_FACT_ADDR 0x57
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#endif
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#if defined (CONFIG_HARD_I2C)
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# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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# define CFG_I2C_SPEED 100000 /* 100 kHz */
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# define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x54
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#define CFG_I2C_FACT_ADDR 0x54
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#endif
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/*
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* Flash configuration, expect one 16 Megabyte Bank at most
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*/
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#define CFG_FLASH_BASE 0xff000000
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#define CFG_FLASH_SIZE 0x01000000
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#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0)
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#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
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#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
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/*
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* DRAM configuration - will be read from VPD later... TODO!
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*/
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#if 0
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/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
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#define CFG_DRAM_DDR 0
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#define CFG_DRAM_EMODE 0
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#define CFG_DRAM_MODE 0x008D
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#define CFG_DRAM_CONTROL 0x514F0000
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#define CFG_DRAM_CONFIG1 0xC2233A00
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#define CFG_DRAM_CONFIG2 0x88B70004
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#define CFG_DRAM_TAP_DEL 0x08
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#define CFG_DRAM_RAM_SIZE 0x19
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#endif
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#if 1
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/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
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#define CFG_DRAM_DDR 0
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#define CFG_DRAM_EMODE 0
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#define CFG_DRAM_MODE 0x00CD
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#define CFG_DRAM_CONTROL 0x514F0000
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#define CFG_DRAM_CONFIG1 0xD2333A00
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#define CFG_DRAM_CONFIG2 0x8AD70004
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#define CFG_DRAM_TAP_DEL 0x08
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#define CFG_DRAM_RAM_SIZE 0x19
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#endif
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/*
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* Environment settings
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*/
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#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
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#define CFG_ENV_OFFSET 0x1000
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#define CFG_ENV_SIZE 0x0700
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/*
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* VPD settings
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*/
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#define CFG_FACT_OFFSET 0x1800
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#define CFG_FACT_SIZE 0x0800
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/*
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* Memory map
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*
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* Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
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*/
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#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT 1
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#endif
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
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#define CONFIG_PHY_ADDR 0x1f
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#define CONFIG_PHY_TYPE 0x79c874
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/*
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* GPIO configuration:
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* PSC1,2,3 predefined as UART
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* PCI disabled
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* Ethernet 100 with MD
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*/
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#define CFG_GPS_PORT_CONFIG 0x00058044
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
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#define CFG_LOAD_ADDR 0x200000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
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#define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
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#define RTC(reg) (0xf0010000+reg)
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/* setup CS2 for M48T08. Must MAP 64kB */
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#define CFG_CS2_START RTC(0)
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#define CFG_CS2_SIZE 0x10000
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/* setup CS2 configuration register: */
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/* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
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/* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
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#define CFG_CS2_CFG 0x00047800
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#else
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#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
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#endif
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/*
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* Various low-level settings
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*/
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#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
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#define CFG_HID0_FINAL HID0_ICE
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#define CFG_BOOTCS_START CFG_FLASH_BASE
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#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
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#define CFG_BOOTCS_CFG 0x00047801
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#define CFG_CS0_START CFG_FLASH_BASE
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#define CFG_CS0_SIZE CFG_FLASH_SIZE
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_DEADCYCLE 0x33333333
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#define CFG_RESET_ADDRESS 0x7f000000
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CONFIG_IDE_RESET 1
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#define CONFIG_IDE_PREINIT
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET (0x005c)
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/* Interval between registers */
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#define CFG_ATA_STRIDE 4
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#endif /* __CONFIG_H */
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