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https://github.com/brain-hackers/u-boot-brain
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3a197b2fe4
Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command is fully finished. The sync() is defined in each CPU's io.h file. For those CPUs which do not need sync for now, a dummy sync() is defined in their io.h as well. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
97 lines
3.2 KiB
C
97 lines
3.2 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_AVR32_IO_H
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#define __ASM_AVR32_IO_H
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#ifdef __KERNEL__
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/*
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* Generic IO read/write. These perform native-endian accesses. Note
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* that some architectures will want to re-define __raw_{read,write}w.
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*/
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extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
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extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
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extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
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extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
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extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
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extern void __raw_readsl(unsigned int addr, void *data, int longlen);
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#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
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#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
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#define __raw_readb(a) (*(volatile unsigned char *)(a))
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#define __raw_readw(a) (*(volatile unsigned short *)(a))
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#define __raw_readl(a) (*(volatile unsigned int *)(a))
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/* As long as I/O is only performed in P4 (or possibly P3), we're safe */
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#define writeb(v,a) __raw_writeb(v,a)
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#define writew(v,a) __raw_writew(v,a)
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#define writel(v,a) __raw_writel(v,a)
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#define readb(a) __raw_readb(a)
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#define readw(a) __raw_readw(a)
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#define readl(a) __raw_readl(a)
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/*
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* Bad read/write accesses...
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*/
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extern void __readwrite_bug(const char *fn);
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* All I/O is memory mapped, so these macros doesn't make very much sense
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*/
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#define outb(v,p) __raw_writeb(v, p)
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#define outw(v,p) __raw_writew(cpu_to_le16(v),p)
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#define outl(v,p) __raw_writel(cpu_to_le32(v),p)
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#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; })
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#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
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#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
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#include <asm/addrspace.h>
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/* virt_to_phys will only work when address is in P1 or P2 */
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static __inline__ unsigned long virt_to_phys(volatile void *address)
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{
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return PHYSADDR(address);
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}
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static __inline__ void * phys_to_virt(unsigned long address)
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{
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return (void *)P1SEGADDR(address);
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}
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#define cached(addr) ((void *)P1SEGADDR(addr))
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#define uncached(addr) ((void *)P2SEGADDR(addr))
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#endif /* __KERNEL__ */
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static inline void sync(void)
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{
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}
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#endif /* __ASM_AVR32_IO_H */
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