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https://github.com/brain-hackers/u-boot-brain
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bf4d0495d2
This patch adds armv7m instruction & data cache support. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
94 lines
3.1 KiB
C
94 lines
3.1 KiB
C
/*
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* (C) Copyright 2010,2011
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* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
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*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef ARMV7M_H
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#define ARMV7M_H
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#if defined(__ASSEMBLY__)
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.syntax unified
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.thumb
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#endif
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/* armv7m fixed base addresses */
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#define V7M_SCS_BASE 0xE000E000
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#define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100)
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#define V7M_SCB_BASE (V7M_SCS_BASE + 0x0D00)
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#define V7M_PROC_FTR_BASE (V7M_SCS_BASE + 0x0D78)
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#define V7M_MPU_BASE (V7M_SCS_BASE + 0x0D90)
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#define V7M_FPU_BASE (V7M_SCS_BASE + 0x0F30)
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#define V7M_CACHE_MAINT_BASE (V7M_SCS_BASE + 0x0F50)
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#define V7M_ACCESS_CNTL_BASE (V7M_SCS_BASE + 0x0F90)
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#define V7M_SCB_VTOR 0x08
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#if !defined(__ASSEMBLY__)
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struct v7m_scb {
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uint32_t cpuid; /* CPUID Base Register */
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uint32_t icsr; /* Interrupt Control and State Register */
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uint32_t vtor; /* Vector Table Offset Register */
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uint32_t aircr; /* App Interrupt and Reset Control Register */
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uint32_t scr; /* offset 0x10: System Control Register */
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uint32_t ccr; /* offset 0x14: Config and Control Register */
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uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */
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uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */
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uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */
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uint32_t shcrs; /* offset 0x24: System Handler Control State */
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uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */
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uint32_t hfsr; /* offset 0x2C: HardFault Status Register */
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uint32_t res; /* offset 0x30: reserved */
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uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */
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uint32_t bfar; /* offset 0x38: BusFault Address Reg */
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uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */
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};
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#define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE)
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#define V7M_AIRCR_VECTKEY 0x5fa
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#define V7M_AIRCR_VECTKEY_SHIFT 16
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#define V7M_AIRCR_ENDIAN (1 << 15)
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#define V7M_AIRCR_PRIGROUP_SHIFT 8
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#define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT)
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#define V7M_AIRCR_SYSRESET (1 << 2)
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#define V7M_ICSR_VECTACT_MSK 0xFF
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#define V7M_CCR_DCACHE 16
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#define V7M_CCR_ICACHE 17
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struct v7m_mpu {
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uint32_t type; /* Type Register */
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uint32_t ctrl; /* Control Register */
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uint32_t rnr; /* Region Number Register */
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uint32_t rbar; /* Region Base Address Register */
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uint32_t rasr; /* Region Attribute and Size Register */
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};
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#define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE)
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#define V7M_MPU_CTRL_ENABLE (1 << 0)
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#define V7M_MPU_CTRL_HFNMIENA (1 << 1)
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#define V7M_MPU_CTRL_ENABLE (1 << 0)
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#define V7M_MPU_CTRL_DISABLE (0 << 0)
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#define V7M_MPU_CTRL_HFNMIENA (1 << 1)
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#define V7M_MPU_RASR_EN (1 << 0)
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#define V7M_MPU_RASR_SIZE_BITS 1
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#define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS)
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#define V7M_MPU_RASR_SIZE_8MB (24 << V7M_MPU_RASR_SIZE_BITS)
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#define V7M_MPU_RASR_TEX_SHIFT 19
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#define V7M_MPU_RASR_S_SHIFT 18
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#define V7M_MPU_RASR_C_SHIFT 17
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#define V7M_MPU_RASR_B_SHIFT 16
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#define V7M_MPU_RASR_AP_RW_RW (3 << 24)
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#define V7M_MPU_RASR_XN_ENABLE (0 << 28)
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#define V7M_MPU_RASR_XN_DISABLE (1 << 28)
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#endif /* !defined(__ASSEMBLY__) */
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#endif /* ARMV7M_H */
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