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https://github.com/brain-hackers/u-boot-brain
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RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
23 lines
884 B
Makefile
23 lines
884 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
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obj-y += timer-uclass.o
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obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
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obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
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obj-$(CONFIG_ARC_TIMER) += arc_timer.o
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obj-$(CONFIG_AST_TIMER) += ast_timer.o
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obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
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obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
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obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
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obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
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obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
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obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
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obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
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obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
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obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
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obj-$(CONFIG_STI_TIMER) += sti-timer.o
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obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
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obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
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obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
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