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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
15 lines
240 B
C
15 lines
240 B
C
/*
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* Copyright (C) 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_XTENSA_RELOCATE_H
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#define _ASM_XTENSA_RELOCATE_H
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#include <common.h>
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int clear_bss(void);
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#endif /* _ASM_XTENSA_RELOCATE_H */
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