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![Dan Murphy](/assets/img/avatar_default.png)
Add the OMAP file for the xHCI Host controller This code will initilialize the proper components within the OMAP5 to enable the xHCI host controller. Signed-off-by: Dan Murphy <dmurphy@ti.com>
327 lines
8.1 KiB
C
327 lines
8.1 KiB
C
/*
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* OMAP USB HOST xHCI Controller
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* Author: Dan Murphy <dmurphy@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <usb.h>
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#include <asm-generic/errno.h>
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#include <asm/omap_common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/xhci-omap.h>
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#include <linux/compat.h>
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#include <linux/usb/dwc3.h>
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#include "xhci.h"
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/* Declare global data pointer */
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DECLARE_GLOBAL_DATA_PTR;
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static struct omap_xhci omap;
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struct usb_dpll_params {
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u16 m;
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u8 n;
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u8 freq:3;
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u8 sd;
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u32 mf;
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};
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#define NUM_USB_CLKS 6
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static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
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{1250, 5, 4, 20, 0}, /* 12 MHz */
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{3125, 20, 4, 20, 0}, /* 16.8 MHz */
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{1172, 8, 4, 20, 65537}, /* 19.2 MHz */
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{1250, 12, 4, 20, 0}, /* 26 MHz */
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{3125, 47, 4, 20, 92843}, /* 38.4 MHz */
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{1000, 7, 4, 10, 0}, /* 20 MHz */
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};
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static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
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{
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u32 val;
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writel(SET_PLL_GO, &phy_regs->pll_go);
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do {
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val = readl(&phy_regs->pll_status);
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if (val & PLL_LOCK)
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break;
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} while (1);
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}
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static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
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{
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u32 clk_index = get_sys_clk_index();
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u32 val;
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val = readl(&phy_regs->pll_config_1);
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val &= ~PLL_REGN_MASK;
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val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
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writel(val, &phy_regs->pll_config_1);
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val = readl(&phy_regs->pll_config_2);
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val &= ~PLL_SELFREQDCO_MASK;
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val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
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writel(val, &phy_regs->pll_config_2);
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val = readl(&phy_regs->pll_config_1);
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val &= ~PLL_REGM_MASK;
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val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
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writel(val, &phy_regs->pll_config_1);
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val = readl(&phy_regs->pll_config_4);
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val &= ~PLL_REGM_F_MASK;
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val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
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writel(val, &phy_regs->pll_config_4);
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val = readl(&phy_regs->pll_config_3);
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val &= ~PLL_SD_MASK;
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val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
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writel(val, &phy_regs->pll_config_3);
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omap_usb_dpll_relock(phy_regs);
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}
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static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
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{
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u32 rate = get_sys_clk_freq()/1000000;
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u32 val;
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val = readl((*ctrl)->control_phy_power_usb);
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val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
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val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
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val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
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writel(val, (*ctrl)->control_phy_power_usb);
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}
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static void usb3_phy_power(int on)
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{
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u32 val;
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val = readl((*ctrl)->control_phy_power_usb);
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if (on) {
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val &= ~USB3_PWRCTL_CLK_CMD_MASK;
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val |= USB3_PHY_TX_RX_POWERON;
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} else {
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val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
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}
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writel(val, (*ctrl)->control_phy_power_usb);
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}
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static void dwc_usb3_phy_init(struct omap_usb3_phy *phy_regs)
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{
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omap_usb_dpll_lock(phy_regs);
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usb3_phy_partial_powerup(phy_regs);
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/*
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* Give enough time for the PHY to partially power-up before
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* powering it up completely. delay value suggested by the HW
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* team.
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*/
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mdelay(100);
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usb3_phy_power(1);
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}
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static void omap_enable_phy_clocks(struct omap_xhci *omap)
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{
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u32 val;
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/* Setting OCP2SCP1 register */
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setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
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OCP2SCP1_CLKCTRL_MODULEMODE_HW);
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/* Turn on 32K AON clk */
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setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
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USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
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/* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
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writel(0x0, (*prcm)->cm_l3init_clkstctrl);
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val = (USBOTGSS_DMADISABLE |
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USBOTGSS_STANDBYMODE_SMRT_WKUP |
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USBOTGSS_IDLEMODE_NOIDLE);
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writel(val, &omap->otg_wrapper->sysconfig);
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/* Clear the utmi OTG status */
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val = readl(&omap->otg_wrapper->utmi_otg_status);
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writel(val, &omap->otg_wrapper->utmi_otg_status);
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/* Enable interrupts */
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writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
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val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
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USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
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USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN |
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USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN |
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USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN |
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USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN |
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USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
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USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
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USBOTGSS_IRQ_SET_1_OEVT_EN);
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writel(val, &omap->otg_wrapper->irqenable_set_1);
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/* Clear the IRQ status */
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val = readl(&omap->otg_wrapper->irqstatus_1);
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writel(val, &omap->otg_wrapper->irqstatus_1);
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val = readl(&omap->otg_wrapper->irqstatus_0);
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writel(val, &omap->otg_wrapper->irqstatus_0);
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/* Enable the USB OTG Super speed clocks */
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val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
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setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
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};
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inline int __board_usb_init(void)
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{
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return 0;
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}
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int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
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static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
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{
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clrsetbits_le32(&dwc3_reg->g_ctl,
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DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
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DWC3_GCTL_PRTCAPDIR(mode));
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}
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static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
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{
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/* Before Resetting PHY, put Core in Reset */
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setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
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/* Assert USB3 PHY reset */
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setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Assert USB2 PHY reset */
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setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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mdelay(100);
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/* Clear USB3 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Clear USB2 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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/* After PHYs are stable we can take Core out of reset state */
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clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
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}
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static int dwc3_core_init(struct dwc3 *dwc3_reg)
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{
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u32 reg;
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u32 revision;
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unsigned int dwc3_hwparams1;
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revision = readl(&dwc3_reg->g_snpsid);
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/* This should read as U3 followed by revision number */
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if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
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puts("this is not a DesignWare USB3 DRD Core\n");
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return -1;
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}
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dwc3_core_soft_reset(dwc3_reg);
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dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
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reg = readl(&dwc3_reg->g_ctl);
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reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
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reg &= ~DWC3_GCTL_DISSCRAMBLE;
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switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
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case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
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reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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break;
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default:
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debug("No power optimization available\n");
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}
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/*
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* WORKAROUND: DWC3 revisions <1.90a have a bug
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* where the device can fail to connect at SuperSpeed
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* and falls back to high-speed mode which causes
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* the device to enter a Connect/Disconnect loop
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*/
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if ((revision & DWC3_REVISION_MASK) < 0x190a)
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reg |= DWC3_GCTL_U2RSTECN;
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writel(reg, &dwc3_reg->g_ctl);
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return 0;
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}
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static int omap_xhci_core_init(struct omap_xhci *omap)
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{
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int ret = 0;
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omap_enable_phy_clocks(omap);
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dwc_usb3_phy_init(omap->usb3_phy);
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ret = dwc3_core_init(omap->dwc3_reg);
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if (ret) {
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debug("%s:failed to initialize core\n", __func__);
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return ret;
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}
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/* We are hard-coding DWC3 core to Host Mode */
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dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
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return ret;
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}
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static void omap_xhci_core_exit(struct omap_xhci *omap)
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{
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usb3_phy_power(0);
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}
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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{
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struct omap_xhci *ctx = &omap;
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int ret = 0;
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ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE;
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
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ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
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ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
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ret = board_usb_init();
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if (ret != 0) {
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puts("Failed to initialize board for USB\n");
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return ret;
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}
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ret = omap_xhci_core_init(ctx);
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if (ret < 0) {
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puts("Failed to initialize xhci\n");
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return ret;
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}
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*hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE);
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*hcor = (struct xhci_hcor *)((uint32_t) *hccr
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+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)*hccr, (uint32_t)*hcor,
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(uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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return ret;
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}
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void xhci_hcd_stop(int index)
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{
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struct omap_xhci *ctx = &omap;
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omap_xhci_core_exit(ctx);
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}
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