mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-17 00:26:16 +09:00
c37207d7f5
U-Boot allows for configurable prompt strings using the CONFIG_AUTOBOOT_PROMPT resp. CONFIG_MENUPROMPT definitions. So far, the assumption was that any such user defined problts would contain exactly one "%d" format specifier. But some boards did not. To allow for flexible boot prompts without adding too complex code we now allow to specify the whole list of printf() arguments in the user definition. This is powerful, but requires a responsible user who really understands what he is doing, as he needs to know for exanple which variables are available in the respective context. Signed-off-by: Wolfgang Denk <wd@denx.de>
450 lines
17 KiB
C
450 lines
17 KiB
C
/*
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* (C) Copyright 2005-2008
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* (C) Copyright 2001-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_APCG405 1 /* ...on a APC405 board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_BOARD_EARLY_INIT_R 1
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */
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#define CONFIG_BOOTCOUNT_LIMIT 1
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#undef CONFIG_BOOTARGS
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#define CFG_USB_LOAD_COMMAND "fatload usb 0 200000 pImage;" \
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"fatload usb 0 300000 pImage.initrd"
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#define CFG_USB_SELF_COMMAND "usb start;run usb_load;usb stop;" \
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"run ramargs addip addcon usbargs;" \
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"bootm 200000 300000"
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#define CFG_USB_ARGS "setenv bootargs $(bootargs) usbboot=1"
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#define CFG_BOOTLIMIT "3"
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#define CFG_ALT_BOOTCOMMAND "run usb_self;reset"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hostname=abg405\0" \
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"bd_type=abg405\0" \
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"serial#=AA0000\0" \
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"kernel_addr=fe000000\0" \
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"ramdisk_addr=fe100000\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath)\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
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":$(hostname)::off panic=1\0" \
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"addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)" \
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" $(optargs)\0" \
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"flash_self=run ramargs addip addcon;" \
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"bootm $(kernel_addr) $(ramdisk_addr)\0" \
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"net_nfs=tftp 200000 $(img);run nfsargs addip addcon;" \
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"bootm\0" \
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"rootpath=/tftpboot/abg405/target_root\0" \
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"img=/tftpboot/abg405/pImage\0" \
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"load=tftp 100000 /tftpboot/abg405/u-boot.bin\0" \
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"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
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"cp.b 100000 fff80000 80000\0" \
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"ipaddr=10.0.111.111\0" \
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"netmask=255.255.0.0\0" \
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"serverip=10.0.0.190\0" \
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"splashimage=ffe80000\0" \
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"usb_load="CFG_USB_LOAD_COMMAND"\0" \
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"usb_self="CFG_USB_SELF_COMMAND"\0" \
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"usbargs="CFG_USB_ARGS"\0" \
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"bootlimit="CFG_BOOTLIMIT"\0" \
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"altbootcmd="CFG_ALT_BOOTCOMMAND"\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self;reset"
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#define CONFIG_ETHADDR 00:02:27:8e:00:00
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_AUTOSCRIPT
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SUPPORT_VFAT
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#define CONFIG_AUTO_UPDATE 1 /* autoupdate via CF or USB */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
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#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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/* Only interrupt boot if space is pressed */
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/* If a long serial cable is connected but */
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/* other end is dead, garbage will be read */
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#undef CONFIG_AUTOBOOT_DELAY_STR
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*
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* PCI stuff
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CONFIG_PCI_SKIP_HOST_BRIDGE 1
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#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
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#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
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#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*
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* IDE/ATA stuff
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*/
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS) /* max. 1 drives per IDE bus */
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#define CFG_ATA_BASE_ADDR 0xF0100000
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
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#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_MONITOR_BASE 0xFFF80000
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#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
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#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Init. Memory map for Linux */
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/*
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* FLASH organization
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*/
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#ifndef __ASSEMBLY__
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extern int flash_banks;
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#endif
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
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#define CFG_MAX_FLASH_BANKS flash_banks /* max num of flash banks */
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/* updated in board_early_init_r */
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#define CFG_MAX_FLASH_BANKS_DETECT 2
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#define CFG_FLASH_QUIET_TEST 1
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#define CFG_FLASH_INCREMENT 0x01000000
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#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
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#define CFG_FLASH_AUTOPROTECT_LIST { \
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{0xfe000000, 0x500000}, \
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{0xffe80000, 0x180000} \
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}
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_BANKS_LIST { \
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CFG_FLASH_BASE, \
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CFG_FLASH_BASE + CFG_FLASH_INCREMENT \
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}
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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/*
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* Environment Variable setup
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*/
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_OFFSET 0x000 /* environment starts at the */
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/* beginning of the EEPROM */
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#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
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#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting vendor vars */
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#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
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#define CFG_NVRAM_SIZE 242 /* NVRAM size */
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/*
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* I2C EEPROM (CAT24WC16) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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/* 16 byte page write mode using*/
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/* last 4 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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/*
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* External Bus Controller (EBC) Setup
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*/
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#define FLASH0_BA (CFG_FLASH_BASE + CFG_FLASH_INCREMENT) /* FLASH 0 BA */
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#define FLASH1_BA CFG_FLASH_BASE /* FLASH 1 Base Address */
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#define CAN_BA 0xF0000000 /* CAN Base Address */
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#define DUART0_BA 0xF0000400 /* DUART Base Address */
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#define DUART1_BA 0xF0000408 /* DUART Base Address */
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#define RTC_BA 0xF0000500 /* RTC Base Address */
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#define PS2_BA 0xF0000600 /* PS/2 Base Address */
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#define CF_BA 0xF0100000 /* CompactFlash Base Address */
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#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */
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#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */
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#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */
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#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */
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#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
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#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */
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/* Memory Bank 0 (Flash Bank 0) initialization */
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#define CFG_EBC_PB0AP 0x92015480
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#define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
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#define CFG_EBC_PB0AP_HWREV8 CFG_EBC_PB0AP
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#define CFG_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
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/* Memory Bank 1 (Flash Bank 1) initialization */
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#define CFG_EBC_PB1AP 0x92015480
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#define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
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/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */
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#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
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#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
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/* Memory Bank 4 (PCMCIA Slot 1) initialization */
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#define CFG_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
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/* Memory Bank 5 (Epson VGA) initialization */
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#define CFG_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
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#define CFG_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
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/* Memory Bank 6 (PCMCIA Slot 2) initialization */
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#define CFG_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
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/*
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* FPGA stuff
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*/
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/* FPGA internal regs */
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#define CFG_FPGA_CTRL 0x008
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#define CFG_FPGA_CTRL2 0x00a
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/* FPGA Control Reg */
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#define CFG_FPGA_CTRL_CF_RESET 0x0001
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#define CFG_FPGA_CTRL_WDI 0x0002
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#define CFG_FPGA_CTRL_PS2_RESET 0x0020
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#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
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#define CFG_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */
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/* FPGA program pin configuration */
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#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
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#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
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#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
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#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
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#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
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/*
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* LCD Setup
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*/
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#define CFG_LCD_BIG_MEM (VGA_BA + 0x200000) /* S1D13806 Mem Base */
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#define CFG_LCD_BIG_REG VGA_BA /* S1D13806 Reg Base */
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#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */
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/* Image information... */
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#define CONFIG_LCD_USED CONFIG_LCD_BIG
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#define CFG_LCD_MEM CFG_LCD_BIG_MEM
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#define CFG_LCD_REG CFG_LCD_BIG_REG
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#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
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/*
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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#define CFG_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CFG_OCM_DATA_ADDR 0xF8000000
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#define CFG_OCM_DATA_SIZE 0x1000
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* reserved bytes for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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/* reserve some memory for BOOT limit info */
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#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
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#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
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#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 8)
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*
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* PCI OHCI controller
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*/
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_PCI_OHCI 1
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#define CFG_OHCI_SWAP_REG_ACCESS 1
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
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#define CONFIG_USB_STORAGE 1
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#define CFG_USB_OHCI_BOARD_INIT 1
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#endif /* __CONFIG_H */
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