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https://github.com/brain-hackers/u-boot-brain
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![Daniel Schwierzeck](/assets/img/avatar_default.png)
All current CPUs and SoCs are based on MIPS32 arch. The complete code resides in the global arch/mips/cpu directory. This is not suitable if other MIPS architectures like MIPS64 or Octeon should be supported in the future. To achieve this the current CPU code is moved to its own mips32 subdirectory. All MIPS32 boards have to use mips32 as config switch in board.cfg. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Lange <thomas@corelatus.se> Cc: Vlad Lungu <vlad.lungu@windriver.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
113 lines
2.7 KiB
C
113 lines
2.7 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mipsregs.h>
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#include <asm/cacheops.h>
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#include <asm/reboot.h>
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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void __attribute__((weak)) _machine_restart(void)
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{
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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_machine_restart();
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fprintf(stderr, "*** reset failed ***\n");
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return 0;
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
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while (1) {
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cache_op(Hit_Writeback_Inv_D, addr);
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cache_op(Hit_Invalidate_I, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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while (1) {
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cache_op(Hit_Writeback_Inv_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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while (1) {
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cache_op(Hit_Invalidate_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
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{
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write_c0_entrylo0(low0);
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write_c0_pagemask(pagemask);
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write_c0_entrylo1(low1);
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write_c0_entryhi(hi);
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write_c0_index(index);
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tlb_write_indexed();
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}
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int cpu_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SOC_AU1X00
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au1x00_enet_initialize(bis);
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#endif
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return 0;
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}
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