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75a8a641f3
At the moment the H6 DRAM driver only supports LPDDR3 DRAM. Extend the driver to cover DDR3 DRAM as well. The changes are partly motivated by looking at the ZynqMP register documentation, partly by looking at register dumps after boot0/libdram has initialised the controller. Many thanks to Jernej for contributing some fixes! Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
333 lines
9.8 KiB
C
333 lines
9.8 KiB
C
/*
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* H6 dram controller register and constant defines
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*
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DRAM_SUN50I_H6_H
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#define _SUNXI_DRAM_SUN50I_H6_H
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#include <stdbool.h>
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enum sunxi_dram_type {
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SUNXI_DRAM_TYPE_DDR3 = 3,
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SUNXI_DRAM_TYPE_DDR4,
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SUNXI_DRAM_TYPE_LPDDR2 = 6,
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SUNXI_DRAM_TYPE_LPDDR3,
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};
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static inline bool sunxi_dram_is_lpddr(int type)
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{
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return type >= SUNXI_DRAM_TYPE_LPDDR2;
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}
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/*
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* The following information is mainly retrieved by disassembly and some FPGA
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* test code of sun50iw3 platform.
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*/
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struct sunxi_mctl_com_reg {
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u32 cr; /* 0x000 control register */
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u8 reserved_0x004[4]; /* 0x004 */
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u32 unk_0x008; /* 0x008 */
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u32 tmr; /* 0x00c timer register */
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u8 reserved_0x010[4]; /* 0x010 */
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u32 unk_0x014; /* 0x014 */
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u8 reserved_0x018[8]; /* 0x018 */
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u32 maer0; /* 0x020 master enable register 0 */
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u32 maer1; /* 0x024 master enable register 1 */
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u32 maer2; /* 0x028 master enable register 2 */
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u8 reserved_0x02c[468]; /* 0x02c */
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u32 bwcr; /* 0x200 bandwidth control register */
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u8 reserved_0x204[12]; /* 0x204 */
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/*
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* The last master configured by BSP libdram is at 0x49x, so the
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* size of this struct array is set to 41 (0x29) now.
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*/
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struct {
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u32 cfg0; /* 0x0 */
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u32 cfg1; /* 0x4 */
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u8 reserved_0x8[8]; /* 0x8 */
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} master[41]; /* 0x210 + index * 0x10 */
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};
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check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498);
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/*
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* The following register information are retrieved from some similar DRAM
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* controllers, including the DRAM controllers in Allwinner A23/A80 SoCs,
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* Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs.
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*
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* The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems
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* to be older than the one in Allwinner H6, as the DRAMTMG9 register
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* is missing in these SoCs. (From the product specifications of these
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* SoCs they're not capable of DDR4)
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*
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* Information sources:
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* - dram_sun9i.h and dram_sun8i_a23.h in the same directory.
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* - sdram_rk3328.h from the RK3328 TPL DRAM patchset
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* - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM)
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* - Zynq UltraScale+ MPSoC Register Reference (UG1087)
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*/
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struct sunxi_mctl_ctl_reg {
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u32 mstr; /* 0x000 */
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u32 statr; /* 0x004 unused */
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u32 mstr1; /* 0x008 unused */
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u32 unk_0x00c; /* 0x00c */
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u32 mrctrl0; /* 0x010 unused */
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u32 mrctrl1; /* 0x014 unused */
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u32 mrstatr; /* 0x018 unused */
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u32 mrctrl2; /* 0x01c unused */
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u32 derateen; /* 0x020 unused */
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u32 derateint; /* 0x024 unused */
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u8 reserved_0x028[8]; /* 0x028 */
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u32 pwrctl; /* 0x030 unused */
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u32 pwrtmg; /* 0x034 unused */
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u32 hwlpctl; /* 0x038 unused */
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u8 reserved_0x03c[20]; /* 0x03c */
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u32 rfshctl0; /* 0x050 unused */
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u32 rfshctl1; /* 0x054 unused */
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u8 reserved_0x058[8]; /* 0x05c */
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u32 rfshctl3; /* 0x060 */
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u32 rfshtmg; /* 0x064 */
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u8 reserved_0x068[104]; /* 0x068 reserved for ECC&CRC (from ZynqMP) */
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u32 init[8]; /* 0x0d0 */
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u32 dimmctl; /* 0x0f0 unused */
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u32 rankctl; /* 0x0f4 */
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u8 reserved_0x0f8[8]; /* 0x0f8 */
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u32 dramtmg[17]; /* 0x100 */
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u8 reserved_0x144[60]; /* 0x144 */
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u32 zqctl[3]; /* 0x180 */
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u32 zqstat; /* 0x18c unused */
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u32 dfitmg0; /* 0x190 */
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u32 dfitmg1; /* 0x194 */
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u32 dfilpcfg[2]; /* 0x198 unused */
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u32 dfiupd[3]; /* 0x1a0 */
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u32 reserved_0x1ac; /* 0x1ac */
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u32 dfimisc; /* 0x1b0 */
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u32 dfitmg2; /* 0x1b4 unused, may not exist */
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u8 reserved_0x1b8[8]; /* 0x1b8 */
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u32 dbictl; /* 0x1c0 */
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u8 reserved_0x1c4[60]; /* 0x1c4 */
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u32 addrmap[12]; /* 0x200 */
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u8 reserved_0x230[16]; /* 0x230 */
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u32 odtcfg; /* 0x240 */
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u32 odtmap; /* 0x244 */
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u8 reserved_0x248[8]; /* 0x248 */
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u32 sched[2]; /* 0x250 */
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u8 reserved_0x258[180]; /* 0x258 */
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u32 dbgcmd; /* 0x30c unused */
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u32 dbgstat; /* 0x310 unused */
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u8 reserved_0x314[12]; /* 0x314 */
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u32 swctl; /* 0x320 */
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u32 swstat; /* 0x324 */
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};
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check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
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#define MSTR_DEVICETYPE_DDR3 BIT(0)
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#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
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#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
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#define MSTR_DEVICETYPE_DDR4 BIT(4)
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#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
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#define MSTR_2TMODE BIT(10)
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#define MSTR_BUSWIDTH_FULL (0 << 12)
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#define MSTR_BUSWIDTH_HALF (1 << 12)
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#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24)
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#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16)
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/*
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* The following register information is based on Zynq UltraScale+
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* MPSoC Register Reference, as it's the currently only known
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* DDR PHY similar to the one used in H6; however although the
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* map is similar, the bit fields definitions are different.
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*
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* Other DesignWare DDR PHY's have similar register names, but the
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* offset and definitions are both different.
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*/
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struct sunxi_mctl_phy_reg {
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u32 ver; /* 0x000 guess based on similar PHYs */
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u32 pir; /* 0x004 */
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u8 reserved_0x008[8]; /* 0x008 */
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/*
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* The ZynqMP manual didn't document PGCR1, however this register
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* exists on H6 and referenced by libdram.
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*/
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u32 pgcr[8]; /* 0x010 */
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/*
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* By comparing the hardware and the ZynqMP manual, the PGSR seems
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* to start at 0x34 on H6.
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*/
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u8 reserved_0x030[4]; /* 0x030 */
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u32 pgsr[3]; /* 0x034 */
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u32 ptr[7]; /* 0x040 */
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/*
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* According to ZynqMP reference there's PLLCR0~6 in this area,
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* but they're tagged "Type B PLL Only" and H6 seems to have
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* no them.
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* 0x080 is not present in ZynqMP reference but it seems to be
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* present on H6.
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*/
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u8 reserved_0x05c[36]; /* 0x05c */
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u32 unk_0x080; /* 0x080 */
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u8 reserved_0x084[4]; /* 0x084 */
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u32 dxccr; /* 0x088 */
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u8 reserved_0x08c[4]; /* 0x08c */
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u32 dsgcr; /* 0x090 */
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u8 reserved_0x094[4]; /* 0x094 */
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u32 odtcr; /* 0x098 */
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u8 reserved_0x09c[4]; /* 0x09c */
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u32 aacr; /* 0x0a0 */
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u8 reserved_0x0a4[32]; /* 0x0a4 */
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u32 gpr1; /* 0x0c4 */
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u8 reserved_0x0c8[56]; /* 0x0c8 */
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u32 dcr; /* 0x100 */
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u8 reserved_0x104[12]; /* 0x104 */
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u32 dtpr[7]; /* 0x110 */
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u8 reserved_0x12c[20]; /* 0x12c */
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u32 rdimmgcr[3]; /* 0x140 */
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u8 reserved_0x14c[4]; /* 0x14c */
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u32 rdimmcr[5]; /* 0x150 */
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u8 reserved_0x164[4]; /* 0x164 */
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u32 schcr[2]; /* 0x168 */
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u8 reserved_0x170[16]; /* 0x170 */
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/*
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* The ZynqMP manual documents MR0~7, 11~14 and 22.
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*/
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u32 mr[23]; /* 0x180 */
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u8 reserved_0x1dc[36]; /* 0x1dc */
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u32 dtcr[2]; /* 0x200 */
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u32 dtar[3]; /* 0x208 */
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u8 reserved_0x214[4]; /* 0x214 */
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u32 dtdr[2]; /* 0x218 */
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u8 reserved_0x220[16]; /* 0x220 */
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u32 dtedr0; /* 0x230 */
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u32 dtedr1; /* 0x234 */
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u32 dtedr2; /* 0x238 */
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u32 vtdr; /* 0x23c */
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u32 catr[2]; /* 0x240 */
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u8 reserved_0x248[8];
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u32 dqsdr[3]; /* 0x250 */
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u32 dtedr3; /* 0x25c */
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u8 reserved_0x260[160]; /* 0x260 */
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u32 dcuar; /* 0x300 */
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u32 dcudr; /* 0x304 */
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u32 dcurr; /* 0x308 */
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u32 dculr; /* 0x30c */
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u32 dcugcr; /* 0x310 */
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u32 dcutpr; /* 0x314 */
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u32 dcusr[2]; /* 0x318 */
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u8 reserved_0x320[444]; /* 0x320 */
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u32 rankidr; /* 0x4dc */
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u32 riocr[6]; /* 0x4e0 */
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u8 reserved_0x4f8[8]; /* 0x4f8 */
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u32 aciocr[6]; /* 0x500 */
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u8 reserved_0x518[8]; /* 0x518 */
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u32 iovcr[2]; /* 0x520 */
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u32 vtcr[2]; /* 0x528 */
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u8 reserved_0x530[16]; /* 0x530 */
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u32 acbdlr[17]; /* 0x540 */
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u32 aclcdlr; /* 0x584 */
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u8 reserved_0x588[24]; /* 0x588 */
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u32 acmdlr[2]; /* 0x5a0 */
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u8 reserved_0x5a8[216]; /* 0x5a8 */
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struct {
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u32 zqcr; /* 0x00 only the first one valid */
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u32 zqpr[2]; /* 0x04 */
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u32 zqdr[2]; /* 0x0c */
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u32 zqor[2]; /* 0x14 */
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u32 zqsr; /* 0x1c */
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} zq[2]; /* 0x680, 0x6a0 */
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u8 reserved_0x6c0[64]; /* 0x6c0 */
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struct {
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u32 gcr[7]; /* 0x00 */
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u8 reserved_0x1c[36]; /* 0x1c */
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u32 bdlr0; /* 0x40 */
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u32 bdlr1; /* 0x44 */
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u32 bdlr2; /* 0x48 */
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u8 reserved_0x4c[4]; /* 0x4c */
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u32 bdlr3; /* 0x50 */
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u32 bdlr4; /* 0x54 */
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u32 bdlr5; /* 0x58 */
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u8 reserved_0x5c[4]; /* 0x5c */
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u32 bdlr6; /* 0x60 */
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u8 reserved_0x64[28]; /* 0x64 */
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u32 lcdlr[6]; /* 0x80 */
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u8 reserved_0x98[8]; /* 0x98 */
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u32 mdlr[2]; /* 0xa0 */
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u8 reserved_0xa8[24]; /* 0xa8 */
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u32 gtr0; /* 0xc0 */
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u8 reserved_0xc4[12]; /* 0xc4 */
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/*
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* DXnRSR0 is not documented in ZynqMP manual but
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* it's used in libdram.
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*/
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u32 rsr[4]; /* 0xd0 */
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u32 gsr[4]; /* 0xe0 */
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u8 reserved_0xf0[16]; /* 0xf0 */
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} dx[4]; /* 0x700, 0x800, 0x900, 0xa00 */
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};
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check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
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#define PIR_INIT BIT(0)
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#define PIR_ZCAL BIT(1)
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#define PIR_CA BIT(2)
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#define PIR_PLLINIT BIT(4)
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#define PIR_DCAL BIT(5)
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#define PIR_PHYRST BIT(6)
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#define PIR_DRAMRST BIT(7)
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#define PIR_DRAMINIT BIT(8)
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#define PIR_WL BIT(9)
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#define PIR_QSGATE BIT(10)
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#define PIR_WLADJ BIT(11)
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#define PIR_RDDSKW BIT(12)
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#define PIR_WRDSKW BIT(13)
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#define PIR_RDEYE BIT(14)
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#define PIR_WREYE BIT(15)
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#define PIR_VREF BIT(17)
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#define PIR_CTLDINIT BIT(18)
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#define PIR_DQS2DQ BIT(20)
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#define PIR_DCALPSE BIT(29)
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#define PIR_ZCALBYP BIT(30)
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#define DCR_LPDDR3 (1 << 0)
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#define DCR_DDR3 (3 << 0)
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#define DCR_DDR4 (4 << 0)
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#define DCR_DDR8BANK BIT(3)
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#define DCR_DDR2T BIT(28)
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/*
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* The delay parameters allow to allegedly specify delay times of some
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* unknown unit for each individual bit trace in each of the four data bytes
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* the 32-bit wide access consists of. Also three control signals can be
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* adjusted individually.
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*/
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#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
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/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */
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#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4)
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/*
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* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN,
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* Termination and Power down
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*/
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#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6)
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struct dram_para {
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u32 clk;
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enum sunxi_dram_type type;
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u8 cols;
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u8 rows;
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u8 ranks;
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const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
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const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
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};
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static inline int ns_to_t(int nanoseconds)
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{
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const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
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return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
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}
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void mctl_set_timing_params(struct dram_para *para);
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#endif /* _SUNXI_DRAM_SUN50I_H6_H */
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