mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-03 16:53:44 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#ifndef _STV0991_CREG_H
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#define _STV0991_CREG_H
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struct stv0991_creg {
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u32 version; /* offset 0x0 */
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u32 hdpctl; /* offset 0x4 */
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u32 hdpval; /* offset 0x8 */
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u32 hdpgposet; /* offset 0xc */
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u32 hdpgpoclr; /* offset 0x10 */
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u32 hdpgpoval; /* offset 0x14 */
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u32 stm_mux; /* offset 0x18 */
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u32 sysctrl_1; /* offset 0x1c */
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u32 sysctrl_2; /* offset 0x20 */
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u32 sysctrl_3; /* offset 0x24 */
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u32 sysctrl_4; /* offset 0x28 */
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u32 reserved_1[0x35]; /* offset 0x2C-0xFC */
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u32 mux1; /* offset 0x100 */
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u32 mux2; /* offset 0x104 */
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u32 mux3; /* offset 0x108 */
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u32 mux4; /* offset 0x10c */
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u32 mux5; /* offset 0x110 */
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u32 mux6; /* offset 0x114 */
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u32 mux7; /* offset 0x118 */
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u32 mux8; /* offset 0x11c */
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u32 mux9; /* offset 0x120 */
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u32 mux10; /* offset 0x124 */
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u32 mux11; /* offset 0x128 */
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u32 mux12; /* offset 0x12c */
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u32 mux13; /* offset 0x130 */
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u32 reserved_2[0x33]; /* offset 0x134-0x1FC */
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u32 cfg_pad1; /* offset 0x200 */
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u32 cfg_pad2; /* offset 0x204 */
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u32 cfg_pad3; /* offset 0x208 */
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u32 cfg_pad4; /* offset 0x20c */
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u32 cfg_pad5; /* offset 0x210 */
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u32 cfg_pad6; /* offset 0x214 */
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u32 cfg_pad7; /* offset 0x218 */
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u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */
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u32 vdd_pad1; /* offset 0x300 */
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u32 vdd_pad2; /* offset 0x304 */
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u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */
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u32 vdd_comp1; /* offset 0x400 */
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};
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/* CREG MUX 13 register */
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#define FLASH_CS_NC_SHIFT 4
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#define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT)
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#define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT)
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#define FLASH_CLK_SHIFT 0
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#define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT)
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#define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT)
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/* CREG MUX 12 register */
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#define GPIOC_30_MUX_SHIFT 24
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#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT)
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#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT)
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#define GPIOC_31_MUX_SHIFT 28
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#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT)
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#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT)
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/* CREG MUX 7 register */
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#define GPIOB_16_MUX_SHIFT 0
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#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT)
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#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT)
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#define GPIOB_17_MUX_SHIFT 4
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#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT)
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#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT)
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/* CREG CFG_PAD6 register */
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#define GPIOC_31_MODE_SHIFT 30
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#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT)
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#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT)
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#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT)
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#define GPIOC_30_MODE_SHIFT 28
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#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT)
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#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT)
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#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
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/* CREG Ethernet pad config */
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#define VDD_ETH_PS_1V8 0
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#define VDD_ETH_PS_2V5 2
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#define VDD_ETH_PS_3V3 3
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#define VDD_ETH_PS_MASK 0x3
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#define VDD_ETH_PS_SHIFT 12
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#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
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#define VDD_ETH_M_PS_SHIFT 28
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#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
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#endif
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