mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-03 08:43:45 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
157 lines
3.3 KiB
C
157 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
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*/
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#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
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#define __ARCH_ARM_MACH_S32V234_DDR_H__
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#define DDR0 0
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#define DDR1 1
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/* DDR offset in MSCR register */
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#define _DDR0_RESET 168
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#define _DDR0_CLK0 169
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#define _DDR0_CAS 170
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#define _DDR0_RAS 171
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#define _DDR0_WE_B 172
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#define _DDR0_CKE0 173
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#define _DDR0_CKE1 174
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#define _DDR0_CS_B0 175
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#define _DDR0_CS_B1 176
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#define _DDR0_BA0 177
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#define _DDR0_BA1 178
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#define _DDR0_BA2 179
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#define _DDR0_A0 180
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#define _DDR0_A1 181
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#define _DDR0_A2 182
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#define _DDR0_A3 183
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#define _DDR0_A4 184
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#define _DDR0_A5 185
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#define _DDR0_A6 186
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#define _DDR0_A7 187
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#define _DDR0_A8 188
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#define _DDR0_A9 189
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#define _DDR0_A10 190
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#define _DDR0_A11 191
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#define _DDR0_A12 192
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#define _DDR0_A13 193
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#define _DDR0_A14 194
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#define _DDR0_A15 195
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#define _DDR0_DM0 196
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#define _DDR0_DM1 197
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#define _DDR0_DM2 198
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#define _DDR0_DM3 199
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#define _DDR0_DQS0 200
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#define _DDR0_DQS1 201
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#define _DDR0_DQS2 202
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#define _DDR0_DQS3 203
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#define _DDR0_D0 204
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#define _DDR0_D1 205
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#define _DDR0_D2 206
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#define _DDR0_D3 207
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#define _DDR0_D4 208
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#define _DDR0_D5 209
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#define _DDR0_D6 210
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#define _DDR0_D7 211
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#define _DDR0_D8 212
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#define _DDR0_D9 213
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#define _DDR0_D10 214
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#define _DDR0_D11 215
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#define _DDR0_D12 216
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#define _DDR0_D13 217
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#define _DDR0_D14 218
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#define _DDR0_D15 219
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#define _DDR0_D16 220
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#define _DDR0_D17 221
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#define _DDR0_D18 222
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#define _DDR0_D19 223
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#define _DDR0_D20 224
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#define _DDR0_D21 225
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#define _DDR0_D22 226
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#define _DDR0_D23 227
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#define _DDR0_D24 228
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#define _DDR0_D25 229
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#define _DDR0_D26 230
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#define _DDR0_D27 231
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#define _DDR0_D28 232
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#define _DDR0_D29 233
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#define _DDR0_D30 234
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#define _DDR0_D31 235
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#define _DDR0_ODT0 236
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#define _DDR0_ODT1 237
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#define _DDR0_ZQ 238
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#define _DDR1_RESET 239
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#define _DDR1_CLK0 240
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#define _DDR1_CAS 241
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#define _DDR1_RAS 242
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#define _DDR1_WE_B 243
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#define _DDR1_CKE0 244
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#define _DDR1_CKE1 245
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#define _DDR1_CS_B0 246
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#define _DDR1_CS_B1 247
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#define _DDR1_BA0 248
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#define _DDR1_BA1 249
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#define _DDR1_BA2 250
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#define _DDR1_A0 251
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#define _DDR1_A1 252
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#define _DDR1_A2 253
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#define _DDR1_A3 254
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#define _DDR1_A4 255
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#define _DDR1_A5 256
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#define _DDR1_A6 257
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#define _DDR1_A7 258
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#define _DDR1_A8 259
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#define _DDR1_A9 260
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#define _DDR1_A10 261
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#define _DDR1_A11 262
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#define _DDR1_A12 263
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#define _DDR1_A13 264
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#define _DDR1_A14 265
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#define _DDR1_A15 266
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#define _DDR1_DM0 267
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#define _DDR1_DM1 268
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#define _DDR1_DM2 269
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#define _DDR1_DM3 270
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#define _DDR1_DQS0 271
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#define _DDR1_DQS1 272
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#define _DDR1_DQS2 273
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#define _DDR1_DQS3 274
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#define _DDR1_D0 275
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#define _DDR1_D1 276
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#define _DDR1_D2 277
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#define _DDR1_D3 278
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#define _DDR1_D4 279
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#define _DDR1_D5 280
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#define _DDR1_D6 281
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#define _DDR1_D7 282
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#define _DDR1_D8 283
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#define _DDR1_D9 284
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#define _DDR1_D10 285
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#define _DDR1_D11 286
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#define _DDR1_D12 287
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#define _DDR1_D13 288
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#define _DDR1_D14 289
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#define _DDR1_D15 290
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#define _DDR1_D16 291
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#define _DDR1_D17 292
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#define _DDR1_D18 293
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#define _DDR1_D19 294
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#define _DDR1_D20 295
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#define _DDR1_D21 296
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#define _DDR1_D22 297
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#define _DDR1_D23 298
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#define _DDR1_D24 299
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#define _DDR1_D25 300
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#define _DDR1_D26 301
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#define _DDR1_D27 302
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#define _DDR1_D28 303
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#define _DDR1_D29 304
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#define _DDR1_D30 305
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#define _DDR1_D31 306
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#define _DDR1_ODT0 307
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#define _DDR1_ODT1 308
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#define _DDR1_ZQ 309
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#endif
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