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![Sricharan](/assets/img/avatar_default.png)
This patch adds the minimal support for OMAP5. The platform and machine specific headers and sources updated for OMAP5430. OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Also moved some part of code from the basic platform support that can be made common for OMAP4/5. Rest is kept out seperately. The same approach is followed for clocks and emif support in the subsequent patches. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
176 lines
4.6 KiB
C
176 lines
4.6 KiB
C
/*
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* (C) Copyright 2006-2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _CPU_H
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#define _CPU_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct gpmc_cs {
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u32 config1; /* 0x00 */
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u32 config2; /* 0x04 */
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u32 config3; /* 0x08 */
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u32 config4; /* 0x0C */
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u32 config5; /* 0x10 */
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u32 config6; /* 0x14 */
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u32 config7; /* 0x18 */
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u32 nand_cmd; /* 0x1C */
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u32 nand_adr; /* 0x20 */
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u32 nand_dat; /* 0x24 */
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u8 res[8]; /* blow up to 0x30 byte */
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};
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struct gpmc {
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u8 res1[0x10];
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u32 sysconfig; /* 0x10 */
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u8 res2[0x4];
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u32 irqstatus; /* 0x18 */
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u32 irqenable; /* 0x1C */
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u8 res3[0x20];
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u32 timeout_control; /* 0x40 */
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u8 res4[0xC];
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u32 config; /* 0x50 */
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u32 status; /* 0x54 */
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u8 res5[0x8]; /* 0x58 */
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struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
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u8 res6[0x14]; /* 0x1E0 */
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u32 ecc_config; /* 0x1F4 */
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u32 ecc_control; /* 0x1F8 */
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u32 ecc_size_config; /* 0x1FC */
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u32 ecc1_result; /* 0x200 */
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u32 ecc2_result; /* 0x204 */
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u32 ecc3_result; /* 0x208 */
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u32 ecc4_result; /* 0x20C */
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u32 ecc5_result; /* 0x210 */
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u32 ecc6_result; /* 0x214 */
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u32 ecc7_result; /* 0x218 */
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u32 ecc8_result; /* 0x21C */
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u32 ecc9_result; /* 0x220 */
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};
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/* Used for board specific gpmc initialization */
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extern struct gpmc *gpmc_cfg;
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struct gptimer {
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u32 tidr; /* 0x00 r */
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u8 res1[0xc];
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u32 tiocp_cfg; /* 0x10 rw */
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u8 res2[0x10];
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u32 tisr_raw; /* 0x24 r */
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u32 tisr; /* 0x28 rw */
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u32 tier; /* 0x2c rw */
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u32 ticr; /* 0x30 rw */
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u32 twer; /* 0x34 rw */
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u32 tclr; /* 0x38 rw */
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u32 tcrr; /* 0x3c rw */
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u32 tldr; /* 0x40 rw */
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u32 ttgr; /* 0x44 rw */
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u32 twpc; /* 0x48 r */
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u32 tmar; /* 0x4c rw */
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u32 tcar1; /* 0x50 r */
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u32 tcicr; /* 0x54 rw */
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u32 tcar2; /* 0x58 r */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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/* enable sys_clk NO-prescale /1 */
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#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
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/* Watchdog */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct watchdog {
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u8 res1[0x34];
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u32 wwps; /* 0x34 r */
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u8 res2[0x10];
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u32 wspr; /* 0x48 rw */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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#define SYSCLKDIV_1 (0x1 << 6)
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#define SYSCLKDIV_2 (0x1 << 7)
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#define CLKSEL_GPT1 (0x1 << 0)
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#define EN_GPT1 (0x1 << 0)
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#define EN_32KSYNC (0x1 << 2)
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#define ST_WDT2 (0x1 << 5)
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#define RESETDONE (0x1 << 0)
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/* GPMC BASE */
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#define GPMC_BASE (OMAP54XX_GPMC_BASE)
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/* I2C base */
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#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000)
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#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000)
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#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000)
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/* MUSB base */
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#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000)
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/* OMAP4 GPIO registers */
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#define OMAP_GPIO_REVISION 0x0000
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#define OMAP_GPIO_SYSCONFIG 0x0010
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#define OMAP_GPIO_SYSSTATUS 0x0114
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#define OMAP_GPIO_IRQSTATUS1 0x0118
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#define OMAP_GPIO_IRQSTATUS2 0x0128
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#define OMAP_GPIO_IRQENABLE2 0x012c
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#define OMAP_GPIO_IRQENABLE1 0x011c
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#define OMAP_GPIO_WAKE_EN 0x0120
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#define OMAP_GPIO_CTRL 0x0130
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#define OMAP_GPIO_OE 0x0134
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#define OMAP_GPIO_DATAIN 0x0138
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#define OMAP_GPIO_DATAOUT 0x013c
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#define OMAP_GPIO_LEVELDETECT0 0x0140
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#define OMAP_GPIO_LEVELDETECT1 0x0144
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#define OMAP_GPIO_RISINGDETECT 0x0148
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#define OMAP_GPIO_FALLINGDETECT 0x014c
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#define OMAP_GPIO_DEBOUNCE_EN 0x0150
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#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
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#define OMAP_GPIO_CLEARIRQENABLE1 0x0160
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#define OMAP_GPIO_SETIRQENABLE1 0x0164
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#define OMAP_GPIO_CLEARWKUENA 0x0180
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#define OMAP_GPIO_SETWKUENA 0x0184
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#define OMAP_GPIO_CLEARDATAOUT 0x0190
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#define OMAP_GPIO_SETDATAOUT 0x0194
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#endif /* _CPU_H */
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