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![Simon Glass](/assets/img/avatar_default.png)
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
192 lines
4.2 KiB
C
192 lines
4.2 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include "clk-uniphier.h"
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/**
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* struct uniphier_clk_priv - private data for UniPhier clock driver
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*
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* @base: base address of the clock provider
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* @data: SoC specific data
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*/
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struct uniphier_clk_priv {
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void __iomem *base;
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const struct uniphier_clk_data *data;
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};
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static int uniphier_clk_enable(struct clk *clk)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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unsigned long id = clk->id;
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const struct uniphier_clk_gate_data *p;
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for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) {
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u32 val;
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if (p->id != id)
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continue;
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val = readl(priv->base + p->reg);
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val |= BIT(p->bit);
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writel(val, priv->base + p->reg);
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return 0;
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}
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dev_err(priv->dev, "clk_id=%lu was not handled\n", id);
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return -EINVAL;
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}
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static const struct uniphier_clk_mux_data *
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uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id)
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{
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const struct uniphier_clk_mux_data *p;
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for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) {
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if (p->id == id)
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return p;
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}
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return NULL;
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}
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static ulong uniphier_clk_get_rate(struct clk *clk)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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const struct uniphier_clk_mux_data *mux;
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u32 val;
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int i;
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mux = uniphier_clk_get_mux_data(priv, clk->id);
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if (!mux)
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return 0;
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if (!mux->nr_muxs) /* fixed-rate */
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return mux->rates[0];
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val = readl(priv->base + mux->reg);
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for (i = 0; i < mux->nr_muxs; i++)
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if ((mux->masks[i] & val) == mux->vals[i])
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return mux->rates[i];
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return -EINVAL;
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}
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static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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const struct uniphier_clk_mux_data *mux;
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u32 val;
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int i, best_rate_id = -1;
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ulong best_rate = 0;
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mux = uniphier_clk_get_mux_data(priv, clk->id);
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if (!mux)
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return 0;
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if (!mux->nr_muxs) /* fixed-rate */
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return mux->rates[0];
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/* first, decide the best match rate */
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for (i = 0; i < mux->nr_muxs; i++) {
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if (mux->rates[i] > best_rate && mux->rates[i] <= rate) {
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best_rate = mux->rates[i];
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best_rate_id = i;
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}
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}
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if (best_rate_id < 0)
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return -EINVAL;
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val = readl(priv->base + mux->reg);
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val &= ~mux->masks[best_rate_id];
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val |= mux->vals[best_rate_id];
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writel(val, priv->base + mux->reg);
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debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
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rate, best_rate);
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return best_rate;
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}
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const struct clk_ops uniphier_clk_ops = {
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.enable = uniphier_clk_enable,
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.get_rate = uniphier_clk_get_rate,
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.set_rate = uniphier_clk_set_rate,
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};
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static int uniphier_clk_probe(struct udevice *dev)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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addr = devfdt_get_addr(dev->parent);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = devm_ioremap(dev, addr, SZ_4K);
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if (!priv->base)
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return -ENOMEM;
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priv->data = (void *)dev_get_driver_data(dev);
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return 0;
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}
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static const struct udevice_id uniphier_clk_match[] = {
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{
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.compatible = "socionext,uniphier-sld3-mio-clock",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld4-mio-clock",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-mio-clock",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-mio-clock",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-sd-clock",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-sd-clock",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-mio-clock",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-sd-clock",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(uniphier_clk) = {
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.name = "uniphier-clk",
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.id = UCLASS_CLK,
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.of_match = uniphier_clk_match,
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.probe = uniphier_clk_probe,
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.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
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.ops = &uniphier_clk_ops,
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};
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