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5e25b9d5d9
PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. [ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| pinctrl-uniphier-core.c | ||
| pinctrl-uniphier-ld4.c | ||
| pinctrl-uniphier-ld6b.c | ||
| pinctrl-uniphier-ld11.c | ||
| pinctrl-uniphier-ld20.c | ||
| pinctrl-uniphier-pro4.c | ||
| pinctrl-uniphier-pro5.c | ||
| pinctrl-uniphier-pxs2.c | ||
| pinctrl-uniphier-sld8.c | ||
| pinctrl-uniphier.h | ||