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https://github.com/brain-hackers/u-boot-brain
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![Prabhakar Kushwaha](/assets/img/avatar_default.png)
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR + IVOR15) to have valid and fetchable OP code. 1) While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to fetch an instruction from the debug exception vector (IVPR + IVOR15); since now we are in AS=0, the application needs to ensure the proper TLB configuration to have (IVOR + IVOR15) accessible from AS=0 also. Create a temporary TLB in AS0 to make sure debug exception verctor is accessible on debug exception. 2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
192 lines
5.7 KiB
C
192 lines
5.7 KiB
C
/*
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* Copyright 2009-2012 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
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void setup_ifc(void)
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{
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struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
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u32 _mas0, _mas1, _mas2, _mas3, _mas7;
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phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
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/*
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* Adjust the TLB we were running out of to match the phys addr of the
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* chip select we are adjusting and will return to.
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*/
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flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
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_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
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_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
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MAS1_TSIZE(BOOKE_PAGESZ_4M);
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_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
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_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
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_mas7 = FSL_BOOKE_MAS7(flash_phys);
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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mtspr(MAS7, _mas7);
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asm volatile("isync;msync;tlbwe;isync");
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#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
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/*
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* TLB entry for debuggging in AS1
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* Create temporary TLB entry in AS0 to handle debug exception
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* As on debug exception MSR is cleared i.e. Address space is changed
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* to 0. A TLB entry (in AS0) is required to handle debug exception generated
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* in AS1.
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*
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* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
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* bacause flash's physical address is going to change as
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* CONFIG_SYS_FLASH_BASE_PHYS.
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*/
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_mas0 = MAS0_TLBSEL(1) |
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MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
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_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
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MAS1_TSIZE(BOOKE_PAGESZ_4M);
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_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
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_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
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_mas7 = FSL_BOOKE_MAS7(flash_phys);
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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mtspr(MAS7, _mas7);
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asm volatile("isync;msync;tlbwe;isync");
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#endif
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/* Change flash's physical address */
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out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
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out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
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out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
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return ;
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}
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#endif
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/* We run cpu_init_early_f in AS = 1 */
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void cpu_init_early_f(void)
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{
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u32 mas0, mas1, mas2, mas3, mas7;
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int i;
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#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
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ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
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u32 *dst, *src;
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void (*setup_ifc_sram)(void);
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#endif
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/*
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* Clear initial global data
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* we don't use memset so we can share this code with NAND_SPL
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*/
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for (i = 0; i < sizeof(gd_t); i++)
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((char *)gd)[i] = 0;
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
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mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
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mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
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write_tlb(mas0, mas1, mas2, mas3, mas7);
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/*
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* Work Around for IFC Erratum A-003549. This issue is P1010
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* specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
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* Hence specifically selecting CS3.
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*/
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#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
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#endif
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init_laws();
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/*
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* Work Around for IFC Erratum A003399, issue will hit only when execution
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* from NOR Flash
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*/
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#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
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#define SRAM_BASE_ADDR (0x00000000)
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/* TLB for SRAM */
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
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MAS1_TSIZE(BOOKE_PAGESZ_1M);
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mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
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mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(0);
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write_tlb(mas0, mas1, mas2, mas3, mas7);
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out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
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out_be32(&l2cache->l2errdis,
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(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
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out_be32(&l2cache->l2ctl,
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(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
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/*
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* Copy the code in setup_ifc to L2SRAM. Do a word copy
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* because NOR Flash on P1010 does not support byte
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* access (Erratum IFC-A002769)
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*/
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setup_ifc_sram = (void *)SRAM_BASE_ADDR;
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dst = (u32 *) SRAM_BASE_ADDR;
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src = (u32 *) setup_ifc;
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for (i = 0; i < 1024; i++)
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*dst++ = *src++;
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setup_ifc_sram();
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/* CLEANUP */
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clrbits_be32(&l2cache->l2ctl,
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(MPC85xx_L2CTL_L2E |
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MPC85xx_L2CTL_L2SRAM_ENTIRE));
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out_be32(&l2cache->l2srbar0, 0x0);
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#endif
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invalidate_tlb(1);
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#if defined(CONFIG_SECURE_BOOT)
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/* Disable the TLBs created by ISBC */
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for (i = CONFIG_SYS_ISBC_START_TLB;
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i < CONFIG_SYS_ISBC_START_TLB + CONFIG_SYS_ISBC_NUM_TLBS; i++)
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disable_tlb(i);
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#endif
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init_tlbs();
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}
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