mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-03 19:33:20 +09:00
745d8a0d3c
This patch implements a fix provided by AMCC so that the lockup upon simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur anymore: Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA. This errata is not officially available yet. I'll update the comment to add the errata number later. Signed-off-by: Stefan Roese <sr@denx.de>
337 lines
9.1 KiB
C
337 lines
9.1 KiB
C
/*
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* (C) Copyright 2000-2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <ppc4xx_enet.h>
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#include <asm/processor.h>
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#include <asm/gpio.h>
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#include <ppc4xx.h>
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#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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#ifndef CFG_PLL_RECONFIG
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#define CFG_PLL_RECONFIG 0
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#endif
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void reconfigure_pll(u32 new_cpu_freq)
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{
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#if defined(CONFIG_440EPX)
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int reset_needed = 0;
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u32 reg, temp;
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u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
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fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
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fbdv, target_fbdv, lfbdv, target_lfbdv,
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perdv0, target_perdv0, /* CLK_PERD */
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spcid0, target_spcid0; /* CLK_SPCID */
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/* Reconfigure clocks if necessary.
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* See PPC440EPx User's Manual, sections 8.2 and 14 */
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if (new_cpu_freq == 667) {
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target_prbdv0 = 2;
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target_fwdva = 2;
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target_fwdvb = 4;
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target_fbdv = 20;
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target_lfbdv = 1;
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target_perdv0 = 4;
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target_spcid0 = 4;
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mfcpr(clk_primbd, reg);
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temp = (reg & PRBDV_MASK) >> 24;
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prbdv0 = temp ? temp : 8;
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if (prbdv0 != target_prbdv0) {
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reg &= ~PRBDV_MASK;
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reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
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mtcpr(clk_primbd, reg);
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reset_needed = 1;
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}
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mfcpr(clk_plld, reg);
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temp = (reg & PLLD_FWDVA_MASK) >> 16;
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fwdva = temp ? temp : 16;
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temp = (reg & PLLD_FWDVB_MASK) >> 8;
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fwdvb = temp ? temp : 8;
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temp = (reg & PLLD_FBDV_MASK) >> 24;
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fbdv = temp ? temp : 32;
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temp = (reg & PLLD_LFBDV_MASK);
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lfbdv = temp ? temp : 64;
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if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
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reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
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PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
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reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
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((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
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((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
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(target_lfbdv == 64 ? 0 : target_lfbdv);
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mtcpr(clk_plld, reg);
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reset_needed = 1;
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}
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mfcpr(clk_perd, reg);
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perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
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if (perdv0 != target_perdv0) {
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reg &= ~CPR0_PERD_PERDV0_MASK;
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reg |= (target_perdv0 << 24);
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mtcpr(clk_perd, reg);
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reset_needed = 1;
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}
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mfcpr(clk_spcid, reg);
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temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
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spcid0 = temp ? temp : 4;
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if (spcid0 != target_spcid0) {
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reg &= ~CPR0_SPCID_SPCIDV0_MASK;
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reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
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mtcpr(clk_spcid, reg);
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reset_needed = 1;
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}
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/* Set reload inhibit so configuration will persist across
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* processor resets */
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mfcpr(clk_icfg, reg);
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reg &= ~CPR0_ICFG_RLI_MASK;
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reg |= 1 << 31;
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mtcpr(clk_icfg, reg);
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}
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/* Reset processor if configuration changed */
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if (reset_needed) {
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__asm__ __volatile__ ("sync; isync");
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mtspr(dbcr0, 0x20000000);
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}
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#endif
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}
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/*
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* Breath some life into the CPU...
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*
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* Reconfigure PLL if necessary,
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* set up the memory map,
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* initialize a bunch of registers
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*/
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void
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cpu_init_f (void)
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{
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#if defined(CONFIG_WATCHDOG) || defined(CONFIG_460EX)
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u32 val;
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#endif
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reconfigure_pll(CFG_PLL_RECONFIG);
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#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
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/*
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* GPIO0 setup (select GPIO or alternate function)
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*/
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#if defined(CFG_GPIO0_OR)
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out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
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#endif
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#if defined(CFG_GPIO0_ODR)
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out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
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#endif
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out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
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out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
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out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
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out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
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out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
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out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
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#if defined(CFG_GPIO0_ISR2H)
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out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
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out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
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#endif
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#if defined (CFG_GPIO0_TCR)
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out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
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#endif
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#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
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#if defined (CONFIG_405EP)
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/*
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* Set EMAC noise filter bits
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*/
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mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
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/*
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* Enable the internal PCI arbiter
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*/
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mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
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#endif /* CONFIG_405EP */
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#if defined(CFG_4xx_GPIO_TABLE)
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gpio_set_chip_configuration();
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#endif /* CFG_4xx_GPIO_TABLE */
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/*
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* External Bus Controller (EBC) Setup
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*/
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#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
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#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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defined(CONFIG_405EX) || defined(CONFIG_405))
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/*
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* Move the next instructions into icache, since these modify the flash
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* we are running from!
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*/
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asm volatile(" bl 0f" ::: "lr");
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asm volatile("0: mflr 3" ::: "r3");
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asm volatile(" addi 4, 0, 14" ::: "r4");
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asm volatile(" mtctr 4" ::: "ctr");
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asm volatile("1: icbt 0, 3");
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asm volatile(" addi 3, 3, 32" ::: "r3");
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asm volatile(" bdnz 1b" ::: "ctr", "cr0");
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asm volatile(" addis 3, 0, 0x0" ::: "r3");
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asm volatile(" ori 3, 3, 0xA000" ::: "r3");
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asm volatile(" mtctr 3" ::: "ctr");
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asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
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#endif
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mtebc(pb0ap, CFG_EBC_PB0AP);
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mtebc(pb0cr, CFG_EBC_PB0CR);
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#endif
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#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
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mtebc(pb1ap, CFG_EBC_PB1AP);
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mtebc(pb1cr, CFG_EBC_PB1CR);
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#endif
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#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
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mtebc(pb2ap, CFG_EBC_PB2AP);
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mtebc(pb2cr, CFG_EBC_PB2CR);
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#endif
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#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
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mtebc(pb3ap, CFG_EBC_PB3AP);
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mtebc(pb3cr, CFG_EBC_PB3CR);
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#endif
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#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
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mtebc(pb4ap, CFG_EBC_PB4AP);
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mtebc(pb4cr, CFG_EBC_PB4CR);
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#endif
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#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
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mtebc(pb5ap, CFG_EBC_PB5AP);
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mtebc(pb5cr, CFG_EBC_PB5CR);
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#endif
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#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
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mtebc(pb6ap, CFG_EBC_PB6AP);
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mtebc(pb6cr, CFG_EBC_PB6CR);
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#endif
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#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
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mtebc(pb7ap, CFG_EBC_PB7AP);
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mtebc(pb7cr, CFG_EBC_PB7CR);
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#endif
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#if defined (CFG_EBC_CFG)
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mtebc(EBC0_CFG, CFG_EBC_CFG);
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#endif
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#if defined(CONFIG_WATCHDOG)
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val = mfspr(tcr);
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
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val |= 0xb8000000; /* generate system reset after 1.34 seconds */
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#elif defined(CONFIG_440EPX)
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val |= 0xb0000000; /* generate system reset after 1.34 seconds */
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#else
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val |= 0xf0000000; /* generate system reset after 2.684 seconds */
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#endif
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#if defined(CFG_4xx_RESET_TYPE)
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val &= ~0x30000000; /* clear WRC bits */
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val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
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#endif
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mtspr(tcr, val);
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val = mfspr(tsr);
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val |= 0x80000000; /* enable watchdog timer */
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mtspr(tsr, val);
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reset_4xx_watchdog();
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_460EX)
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/*
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* Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
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* clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
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* regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
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*/
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mfsdr(SDR0_AHB_CFG, val);
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val |= 0x80;
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val &= ~0x40;
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mtsdr(SDR0_AHB_CFG, val);
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mfsdr(SDR0_USB2HOST_CFG, val);
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val &= ~0xf00;
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val |= 0x400;
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mtsdr(SDR0_USB2HOST_CFG, val);
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#endif /* CONFIG_460EX */
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}
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/*
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* initialize higher level parts of CPU like time base and timers
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*/
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int cpu_init_r (void)
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{
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#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
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bd_t *bd = gd->bd;
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unsigned long reg;
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#if defined(CONFIG_405GP)
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uint pvr = get_pvr();
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#endif
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/*
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* Write Ethernetaddress into on-chip register
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*/
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reg = 0x00000000;
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reg |= bd->bi_enetaddr[0]; /* set high address */
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reg = reg << 8;
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reg |= bd->bi_enetaddr[1];
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out32 (EMAC_IAH, reg);
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reg = 0x00000000;
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reg |= bd->bi_enetaddr[2]; /* set low address */
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reg = reg << 8;
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reg |= bd->bi_enetaddr[3];
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reg = reg << 8;
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reg |= bd->bi_enetaddr[4];
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reg = reg << 8;
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reg |= bd->bi_enetaddr[5];
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out32 (EMAC_IAL, reg);
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#if defined(CONFIG_405GP)
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/*
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* Set edge conditioning circuitry on PPC405GPr
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* for compatibility to existing PPC405GP designs.
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*/
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if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
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mtdcr(ecr, 0x60606000);
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}
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#endif /* defined(CONFIG_405GP) */
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#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
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return (0);
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}
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