mirror of
https://github.com/brain-hackers/u-boot-brain
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68 lines
2.1 KiB
C
68 lines
2.1 KiB
C
/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*
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* CAUTION: This file is automatically generated by libgen.
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* Version: Xilinx EDK 6.3 EDK_Gmm.12.3
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*/
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/* System Clock Frequency */
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#define XILINX_CLOCK_FREQ 66666667
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/* Interrupt controller is intc_0 */
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#define XILINX_INTC_BASEADDR 0xd1000fc0
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#define XILINX_INTC_NUM_INTR_INPUTS 12
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/* Timer pheriphery is opb_timer_0 */
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#define XILINX_TIMER_BASEADDR 0xa2000000
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#define XILINX_TIMER_IRQ 0
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/* Uart pheriphery is console_uart */
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#define XILINX_UART_BASEADDR 0xa0000000
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#define XILINX_UART_BAUDRATE 115200
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/* GPIO is opb_gpio_0*/
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#define XILINX_GPIO_BASEADDR 0x90000000
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/* Flash Memory is opb_emc_0 */
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#define XILINX_FLASH_START 0x28000000
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#define XILINX_FLASH_SIZE 0x00800000
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/* Main Memory is plb_ddr_0 */
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#define XILINX_RAM_START 0x10000000
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#define XILINX_RAM_SIZE 0x10000000
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/* Sysace Controller is opb_sysace_0 */
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#define XILINX_SYSACE_BASEADDR 0xCF000000
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#define XILINX_SYSACE_HIGHADDR 0xCF0001FF
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#define XILINX_SYSACE_MEM_WIDTH 16
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/* Ethernet controller is opb_ethernet_0 */
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#define XPAR_XEMAC_NUM_INSTANCES 1
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#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
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#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
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#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
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#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
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#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
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#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
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