mirror of
https://github.com/brain-hackers/u-boot-brain
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46263f2de4
This commit adapts the files that were derived from PIBS (PowerPC Initialization and Boot Software) codeto using SPDX License Identifiers. So far, SPDX has not assigned an official License ID for the PIBS license yet, so this should be considered preliminary. Note that the following files contained incorrect license information: arch/powerpc/cpu/ppc4xx/4xx_uart.c arch/powerpc/cpu/ppc4xx/start.S arch/powerpc/include/asm/ppc440.h These files included, in addition to the GPL-2.0 / ibm-pibs dual license as inherited from PIBS, a GPL-2.0+ license header which was obviously incorrect. This has been removed. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Conflicts: Licenses/README Acked-by: Stefan Roese <sr@denx.de>
120 lines
4.4 KiB
ArmAsm
120 lines
4.4 KiB
ArmAsm
/*
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* SPDX-License-Identifier: GPL-2.0 ibm-pibs
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*/
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/*----------------------------------------------------------------------------- */
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/* Function: ext_bus_cntlr_init */
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/* Description: Initializes the External Bus Controller for the external */
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/* peripherals. IMPORTANT: For pass1 this code must run from */
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/* cache since you can not reliably change a peripheral banks */
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/* timing register (pbxap) while running code from that bank. */
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/* For ex., since we are running from ROM on bank 0, we can NOT */
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/* execute the code that modifies bank 0 timings from ROM, so */
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/* we run it from cache. */
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/* Bank 0 - Flash and SRAM */
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/* Bank 1 - NVRAM/RTC */
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/* Bank 2 - Keyboard/Mouse controller */
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/* Bank 3 - IR controller */
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/* Bank 4 - not used */
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/* Bank 5 - not used */
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/* Bank 6 - not used */
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/* Bank 7 - FPGA registers */
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/*-----------------------------------------------------------------------------#include <config.h> */
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#include <asm/ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
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/* except for #1 which we use for DMA'ing to IOCA-like things, so the */
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/* control registers to set that up are determined by what we've */
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/* empirically discovered work there. */
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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mflr r4 /* save link register */
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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mtlr r4 /* restore link register */
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addi r4,0,14 /* set ctr to 10; used to prefetch */
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mtctr r4 /* 10 cache lines to fit this function */
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/* in cache (gives us 8x10=80 instrctns) */
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..ebcloop:
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icbt r0,r3 /* prefetch cache line for addr in r3 */
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addi r3,r3,32 /* move to next cache line */
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bdnz ..ebcloop /* continue for 10 cache lines */
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/*------------------------------------------------------------------- */
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/* Delay to ensure all accesses to ROM are complete before changing */
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/* bank 0 timings. 200usec should be enough. */
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/* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
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/*------------------------------------------------------------------- */
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addis r3,0,0x0
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ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
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mtctr r3
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..spinlp:
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bdnz ..spinlp /* spin loop */
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/*---------------------------------------------------------------------- */
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/* Peripheral Bank 0 (Flash) initialization */
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/*---------------------------------------------------------------------- */
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/* 0x7F8FFE80 slowest boot */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x9B01
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ori r4,r4,0x5480
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
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ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
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mtdcr EBC0_CFGDATA,r4
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blr
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/*---------------------------------------------------------------------- */
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/* Peripheral Bank 1 (NVRAM/RTC) initialization */
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/* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
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/* and we do DMA on it. The ConfigurationRegister part is threfore */
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/* almost arbitrary, except that our linux driver needs to know the */
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/* address, but it can query, it.. */
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/* */
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/* The AccessParameter is CRITICAL, */
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/* thouch, since it needs to agree with the electrical timings on the */
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/* IOCA parallel interface. That value is: 0x0185,4380 */
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/* BurstModeEnable BME=0 */
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/* TransferWait TWT=3 */
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/* ChipSelectOnTiming CSN=1 */
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/* OutputEnableOnTimimg OEN=1 */
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/* WriteByteEnableOnTiming WBN=1 */
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/* WriteByteEnableOffTiming WBF=0 */
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/* TransferHold TH=1 */
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/* ReadyEnable RE=1 */
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/* SampleOnReady SOR=1 */
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/* ByteEnableMode BEM=0 */
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/* ParityEnable PEN=0 */
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/* all reserved bits=0 */
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/*---------------------------------------------------------------------- */
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/*---------------------------------------------------------------------- */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0185 /* hiword */
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ori r4,r4,0x4380 /* loword */
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB1CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
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ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
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mtdcr EBC0_CFGDATA,r4
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blr
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